[llvm-commits] [llvm] r117674 - /llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp

[Evan Cheng]

Author: evancheng
Date: Fri Oct 29 13:07:31 2010
New Revision: 117674

URL: http://llvm.org/viewvc/llvm-project?rev=117674&view=rev
Log:
- Don't schedule nodes with only MVT::Flag and MVT::Other values for latency.
- Compute CopyToReg use operand latency correctly.

Modified:
    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=117674&r1=117673&r2=117674&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Fri Oct 29 13:07:31 2010
@@ -855,6 +855,8 @@
 
   for (unsigned i = 0; i != NumVals; ++i) {
     EVT VT = N->getValueType(i);
+    if (VT == MVT::Flag || VT == MVT::Other)
+      continue;
     if (VT.isFloatingPoint() || VT.isVector())
       return Sched::Latency;
   }
@@ -866,11 +868,13 @@
   // is not available.
   const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
   const TargetInstrDesc &TID = TII->get(N->getMachineOpcode());
-  if (TID.mayLoad())
-    return Sched::Latency;
 
-  if (!Itins->isEmpty() && Itins->getStageLatency(TID.getSchedClass()) > 2)
+  if (TID.getNumDefs() == 0)
+    return Sched::RegPressure;
+  if (!Itins->isEmpty() &&
+      Itins->getOperandCycle(TID.getSchedClass(), 0) > 2)
     return Sched::Latency;
+
   return Sched::RegPressure;
 }