[llvm-commits] [llvm] r117626 - in /llvm/trunk: lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/AsmParser/ARMAsmParser.cpp test/MC/ARM/arm_instructions.s
Chris Lattner
sabre at nondot.org
Thu Oct 28 17:27:31 PDT 2010
Author: lattner
Date: Thu Oct 28 19:27:31 2010
New Revision: 117626
URL: http://llvm.org/viewvc/llvm-project?rev=117626&view=rev
Log:
add simple support for addrmode5 operands, allowing
vldr.64 to work. I have no idea if this is fully right, but
it is in the right direction.
Modified:
llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
llvm/trunk/test/MC/ARM/arm_instructions.s
Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=117626&r1=117625&r2=117626&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Thu Oct 28 19:27:31 2010
@@ -456,12 +456,18 @@
let MIOperandInfo = (ops GPR:$addr, i32imm);
}
+def ARMMemMode5AsmOperand : AsmOperandClass {
+ let Name = "MemMode5";
+ let SuperClasses = [];
+}
+
// addrmode5 := reg +/- imm8*4
//
def addrmode5 : Operand<i32>,
ComplexPattern<i32, 2, "SelectAddrMode5", []> {
let PrintMethod = "printAddrMode5Operand";
let MIOperandInfo = (ops GPR:$base, i32imm);
+ let ParserMatchClass = ARMMemMode5AsmOperand;
}
// addrmode6 := reg with optional writeback
Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=117626&r1=117625&r2=117626&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Thu Oct 28 19:27:31 2010
@@ -153,9 +153,6 @@
};
- //ARMOperand(KindTy K, SMLoc S, SMLoc E)
- // : Kind(K), StartLoc(S), EndLoc(E) {}
-
ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
Kind = o.Kind;
StartLoc = o.StartLoc;
@@ -205,16 +202,16 @@
}
bool isCondCode() const { return Kind == CondCode; }
-
bool isImm() const { return Kind == Immediate; }
-
bool isReg() const { return Kind == Register; }
-
- bool isToken() const {return Kind == Token; }
+ bool isToken() const { return Kind == Token; }
+ bool isMemory() const { return Kind == Memory; }
void addExpr(MCInst &Inst, const MCExpr *Expr) const {
- // Add as immediates when possible.
- if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
+ // Add as immediates when possible. Null MCExpr = 0.
+ if (Expr == 0)
+ Inst.addOperand(MCOperand::CreateImm(0));
+ else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
else
Inst.addOperand(MCOperand::CreateExpr(Expr));
@@ -236,6 +233,24 @@
assert(N == 1 && "Invalid number of operands!");
addExpr(Inst, getImm());
}
+
+
+ bool isMemMode5() const {
+ // FIXME: Is this right? What about postindexed and Writeback?
+ if (!isMemory() || Mem.OffsetIsReg || Mem.OffsetRegShifted ||
+ Mem.Preindexed || Mem.Negative)
+ return false;
+
+ return true;
+ }
+
+ void addMemMode5Operands(MCInst &Inst, unsigned N) const {
+ assert(N == 2 && isMemMode5() && "Invalid number of operands!");
+
+ Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
+ assert(!Mem.OffsetIsReg && "invalid mode 5 operand");
+ addExpr(Inst, Mem.Offset);
+ }
virtual void dump(raw_ostream &OS) const;
@@ -508,7 +523,7 @@
bool OffsetRegShifted = false;
enum ShiftType ShiftType;
const MCExpr *ShiftAmount;
- const MCExpr *Offset;
+ const MCExpr *Offset = 0;
const AsmToken &NextTok = Parser.getTok();
if (NextTok.isNot(AsmToken::EndOfStatement)) {
Modified: llvm/trunk/test/MC/ARM/arm_instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/arm_instructions.s?rev=117626&r1=117625&r2=117626&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/arm_instructions.s (original)
+++ llvm/trunk/test/MC/ARM/arm_instructions.s Thu Oct 28 19:27:31 2010
@@ -16,3 +16,7 @@
@ CHECK: encoding: [0xa0,0x0d,0xe1,0xf2]
vqdmull.s32 q8, d17, d16
+@ CHECK: vldr.64 d17, [r0]
+@ CHECK: encoding: [0x00,0x0b,0x10,0xed]
+vldr.64 d17, [r0]
+
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