[llvm-commits] [llvm] r117060 - in /llvm/trunk/lib/Target/ARM: ARMBaseInfo.h ARMMCCodeEmitter.cpp

[Jim Grosbach]

Excellent. Thanks!

On Oct 21, 2010, at 1:49 PM, Owen Anderson wrote:

> Author: resistor
> Date: Thu Oct 21 15:49:13 2010
> New Revision: 117060
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=117060&view=rev
> Log:
> Move the encoding logic for Q registers into getMachineOpValue().
> 
> Modified:
>    llvm/trunk/lib/Target/ARM/ARMBaseInfo.h
>    llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp
> 
> Modified: llvm/trunk/lib/Target/ARM/ARMBaseInfo.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInfo.h?rev=117060&r1=117059&r2=117060&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMBaseInfo.h (original)
> +++ llvm/trunk/lib/Target/ARM/ARMBaseInfo.h Thu Oct 21 15:49:13 2010
> @@ -132,37 +132,37 @@
>   default:
>     llvm_unreachable("Unknown ARM register!");
>   case R0:  case S0:  case D0:  case Q0:  return 0;
> -  case R1:  case S1:  case D1:  return 1;
> -  case R2:  case S2:  case D2:  case Q1:  return 2;
> -  case R3:  case S3:  case D3:  return 3;
> -  case R4:  case S4:  case D4:  case Q2:  return 4;
> -  case R5:  case S5:  case D5:  return 5;
> -  case R6:  case S6:  case D6:  case Q3:  return 6;
> -  case R7:  case S7:  case D7:  return 7;
> -  case R8:  case S8:  case D8:  case Q4:  return 8;
> -  case R9:  case S9:  case D9:  return 9;
> -  case R10: case S10: case D10: case Q5: return 10;
> -  case R11: case S11: case D11: return 11;
> -  case R12: case S12: case D12: case Q6: return 12;
> -  case SP:  case S13: case D13: return 13;
> -  case LR:  case S14: case D14: case Q7: return 14;
> -  case PC:  case S15: case D15: return 15;
> +  case R1:  case S1:  case D1:  case Q1:  return 1;
> +  case R2:  case S2:  case D2:  case Q2:  return 2;
> +  case R3:  case S3:  case D3:  case Q3:  return 3;
> +  case R4:  case S4:  case D4:  case Q4:  return 4;
> +  case R5:  case S5:  case D5:  case Q5:  return 5;
> +  case R6:  case S6:  case D6:  case Q6:  return 6;
> +  case R7:  case S7:  case D7:  case Q7:  return 7;
> +  case R8:  case S8:  case D8:  case Q8:  return 8;
> +  case R9:  case S9:  case D9:  case Q9:  return 9;
> +  case R10: case S10: case D10: case Q10: return 10;
> +  case R11: case S11: case D11: case Q11: return 11;
> +  case R12: case S12: case D12: case Q12: return 12;
> +  case SP:  case S13: case D13: case Q13: return 13;
> +  case LR:  case S14: case D14: case Q14: return 14;
> +  case PC:  case S15: case D15: case Q15: return 15;
> 
> -  case S16: case D16: case Q8: return 16;
> +  case S16: case D16: return 16;
>   case S17: case D17: return 17;
> -  case S18: case D18: case Q9: return 18;
> +  case S18: case D18: return 18;
>   case S19: case D19: return 19;
> -  case S20: case D20: case Q10: return 20;
> +  case S20: case D20: return 20;
>   case S21: case D21: return 21;
> -  case S22: case D22: case Q11: return 22;
> +  case S22: case D22: return 22;
>   case S23: case D23: return 23;
> -  case S24: case D24: case Q12: return 24;
> +  case S24: case D24: return 24;
>   case S25: case D25: return 25;
> -  case S26: case D26: case Q13: return 26;
> +  case S26: case D26: return 26;
>   case S27: case D27: return 27;
> -  case S28: case D28: case Q14: return 28;
> +  case S28: case D28: return 28;
>   case S29: case D29: return 29;
> -  case S30: case D30: case Q15: return 30;
> +  case S30: case D30: return 30;
>   case S31: case D31: return 31;
>   }
> }
> 
> Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp?rev=117060&r1=117059&r2=117060&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Thu Oct 21 15:49:13 2010
> @@ -143,7 +143,18 @@
> unsigned ARMMCCodeEmitter::getMachineOpValue(const MCInst &MI,
>                                              const MCOperand &MO) const {
>   if (MO.isReg()) {
> -    return getARMRegisterNumbering(MO.getReg());
> +    unsigned regno = getARMRegisterNumbering(MO.getReg());
> +    
> +    // Q registers are encodes as 2x their register number.
> +    switch (MO.getReg()) {
> +      case ARM::Q0: case ARM::Q1: case ARM::Q2: case ARM::Q3:
> +      case ARM::Q4: case ARM::Q5: case ARM::Q6: case ARM::Q7:
> +      case ARM::Q8: case ARM::Q9: case ARM::Q10: case ARM::Q11:
> +      case ARM::Q12: case ARM::Q13: case ARM::Q14: case ARM::Q15:
> +        return 2 * regno;
> +      default:
> +        return regno;
> +    }
>   } else if (MO.isImm()) {
>     return static_cast<unsigned>(MO.getImm());
>   } else if (MO.isFPImm()) {
> 
> 
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