[llvm-commits] [llvm] r117039 - in /llvm/trunk: lib/Target/ARM/ARMInstrNEON.td test/MC/ARM/neon-fp-encoding.ll
Owen Anderson
resistor at mac.com
Thu Oct 21 11:09:17 PDT 2010
Author: resistor
Date: Thu Oct 21 13:09:17 2010
New Revision: 117039
URL: http://llvm.org/viewvc/llvm-project?rev=117039&view=rev
Log:
Provide correct NEON encodings for vaddl.u* and vaddl.s*.
Modified:
llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
llvm/trunk/test/MC/ARM/neon-fp-encoding.ll
Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=117039&r1=117038&r2=117039&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Thu Oct 21 13:09:17 2010
@@ -1232,23 +1232,23 @@
InstrItinClass itin, string OpcodeStr, string Dt,
ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
: N3V<op24, op23, op21_20, op11_8, 1, op4,
- (outs QPR:$Dd), (ins QPR:$Dn, QPR:$Dm), N3RegFrm, itin,
- OpcodeStr, Dt, "$Dd, $Dn, $Dm", "",
- [(set QPR:$Dd, (ResTy (OpNode (OpTy QPR:$Dn), (OpTy QPR:$Dm))))]> {
+ (outs QPR:$Qd), (ins QPR:$Qn, QPR:$Qm), N3RegFrm, itin,
+ OpcodeStr, Dt, "$Qd, $Qn, $Qm", "",
+ [(set QPR:$Qd, (ResTy (OpNode (OpTy QPR:$Qn), (OpTy QPR:$Qm))))]> {
let isCommutable = Commutable;
- bits<4> Dd;
- bits<4> Dn;
- bits<4> Dm;
+ bits<4> Qd;
+ bits<4> Qn;
+ bits<4> Qm;
- let Inst{15-13} = Dd{2-0};
- let Inst{22} = Dd{3};
+ let Inst{15-13} = Qd{2-0};
+ let Inst{22} = Qd{3};
let Inst{12} = 0;
- let Inst{19-17} = Dn{2-0};
- let Inst{7} = Dn{3};
+ let Inst{19-17} = Qn{2-0};
+ let Inst{7} = Qn{3};
let Inst{16} = 0;
- let Inst{3-1} = Dm{2-0};
- let Inst{5} = Dm{3};
+ let Inst{3-1} = Qm{2-0};
+ let Inst{5} = Qm{3};
let Inst{0} = 0;
}
class N3VQX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
@@ -1597,10 +1597,25 @@
ValueType TyQ, ValueType TyD, SDNode OpNode, SDNode ExtOp,
bit Commutable>
: N3V<op24, op23, op21_20, op11_8, 0, op4,
- (outs QPR:$dst), (ins DPR:$src1, DPR:$src2), N3RegFrm, itin,
- OpcodeStr, Dt, "$dst, $src1, $src2", "",
- [(set QPR:$dst, (OpNode (TyQ (ExtOp (TyD DPR:$src1))),
- (TyQ (ExtOp (TyD DPR:$src2)))))]> {
+ (outs QPR:$Qd), (ins DPR:$Dn, DPR:$Dm), N3RegFrm, itin,
+ OpcodeStr, Dt, "$Qd, $Dn, $Dm", "",
+ [(set QPR:$Qd, (OpNode (TyQ (ExtOp (TyD DPR:$Dn))),
+ (TyQ (ExtOp (TyD DPR:$Dm)))))]> {
+ let isCommutable = Commutable;
+
+ // Instruction operands.
+ bits<4> Qd;
+ bits<5> Dn;
+ bits<5> Dm;
+
+ let Inst{15-13} = Qd{2-0};
+ let Inst{22} = Qd{3};
+ let Inst{12} = 0;
+ let Inst{19-16} = Dn{3-0};
+ let Inst{7} = Dn{4};
+ let Inst{3-0} = Dm{3-0};
+ let Inst{5} = Dm{4};
+
let isCommutable = Commutable;
}
Modified: llvm/trunk/test/MC/ARM/neon-fp-encoding.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-fp-encoding.ll?rev=117039&r1=117038&r2=117039&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neon-fp-encoding.ll (original)
+++ llvm/trunk/test/MC/ARM/neon-fp-encoding.ll Thu Oct 21 13:09:17 2010
@@ -54,3 +54,68 @@
ret <4 x float> %tmp3
}
+; CHECK: vaddls_8xi8
+define <8 x i16> @vaddls_8xi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = sext <8 x i8> %tmp1 to <8 x i16>
+ %tmp4 = sext <8 x i8> %tmp2 to <8 x i16>
+; CHECK: vaddl.s8 q8, d17, d16 @ encoding: [0xa0,0x00,0xc1,0xf2]
+ %tmp5 = add <8 x i16> %tmp3, %tmp4
+ ret <8 x i16> %tmp5
+}
+
+; CHECK: vaddls_4xi16
+define <4 x i32> @vaddls_4xi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = sext <4 x i16> %tmp1 to <4 x i32>
+ %tmp4 = sext <4 x i16> %tmp2 to <4 x i32>
+; CHECK: vaddl.s16 q8, d17, d16 @ encoding: [0xa0,0x00,0xd1,0xf2]
+ %tmp5 = add <4 x i32> %tmp3, %tmp4
+ ret <4 x i32> %tmp5
+}
+
+; CHECK: vaddls_2xi32
+define <2 x i64> @vaddls_2xi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = sext <2 x i32> %tmp1 to <2 x i64>
+ %tmp4 = sext <2 x i32> %tmp2 to <2 x i64>
+; CHECK: vaddl.s32 q8, d17, d16 @ encoding: [0xa0,0x00,0xe1,0xf2]
+ %tmp5 = add <2 x i64> %tmp3, %tmp4
+ ret <2 x i64> %tmp5
+}
+
+; CHECK: vaddlu_8xi8
+define <8 x i16> @vaddlu_8xi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = zext <8 x i8> %tmp1 to <8 x i16>
+ %tmp4 = zext <8 x i8> %tmp2 to <8 x i16>
+; CHECK: vaddl.u8 q8, d17, d16 @ encoding: [0xa0,0x00,0xc1,0xf3]
+ %tmp5 = add <8 x i16> %tmp3, %tmp4
+ ret <8 x i16> %tmp5
+}
+
+; CHECK: vaddlu_4xi16
+define <4 x i32> @vaddlu_4xi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = zext <4 x i16> %tmp1 to <4 x i32>
+ %tmp4 = zext <4 x i16> %tmp2 to <4 x i32>
+; CHECK: vaddl.u16 q8, d17, d16 @ encoding: [0xa0,0x00,0xd1,0xf3]
+ %tmp5 = add <4 x i32> %tmp3, %tmp4
+ ret <4 x i32> %tmp5
+}
+
+; CHECK: vaddlu_2xi32
+define <2 x i64> @vaddlu_2xi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = zext <2 x i32> %tmp1 to <2 x i64>
+ %tmp4 = zext <2 x i32> %tmp2 to <2 x i64>
+; CHECK: vaddl.u32 q8, d17, d16 @ encoding: [0xa0,0x00,0xe1,0xf3]
+ %tmp5 = add <2 x i64> %tmp3, %tmp4
+ ret <2 x i64> %tmp5
+}
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