[llvm-commits] [llvm] r116970 - in /llvm/trunk: lib/Target/ARM/ARMInstrVFP.td test/MC/ARM/simple-fp-encoding.ll

[Bill Wendling]

Author: void
Date: Wed Oct 20 18:37:40 2010
New Revision: 116970

URL: http://llvm.org/viewvc/llvm-project?rev=116970&view=rev
Log:
Add encoding for moving a value between two ARM core registers and a doublework
extension register.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrVFP.td
    llvm/trunk/test/MC/ARM/simple-fp-encoding.ll

Modified: llvm/trunk/lib/Target/ARM/ARMInstrVFP.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrVFP.td?rev=116970&r1=116969&r2=116970&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrVFP.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Wed Oct 20 18:37:40 2010
@@ -505,9 +505,20 @@
 
 let neverHasSideEffects = 1 in {
 def VMOVRRD  : AVConv3I<0b11000101, 0b1011,
-                      (outs GPR:$wb, GPR:$dst2), (ins DPR:$src),
-                 IIC_fpMOVDI, "vmov", "\t$wb, $dst2, $src",
+                        (outs GPR:$Rt, GPR:$Rt2), (ins DPR:$Dm),
+                        IIC_fpMOVDI, "vmov", "\t$Rt, $Rt2, $Dm",
                  [/* FIXME: Can't write pattern for multiple result instr*/]> {
+  // Instruction operands.
+  bits<5> Dm;
+  bits<4> Rt;
+  bits<4> Rt2;
+
+  // Encode instruction operands.
+  let Inst{3-0}   = Dm{3-0};
+  let Inst{5}     = Dm{4};
+  let Inst{15-12} = Rt;
+  let Inst{19-16} = Rt2;
+
   let Inst{7-6} = 0b00;
 }
 
@@ -523,10 +534,21 @@
 // FMDLR: GPR -> SPR
 
 def VMOVDRR : AVConv5I<0b11000100, 0b1011,
-                     (outs DPR:$dst), (ins GPR:$src1, GPR:$src2),
-                IIC_fpMOVID, "vmov", "\t$dst, $src1, $src2",
-                [(set DPR:$dst, (arm_fmdrr GPR:$src1, GPR:$src2))]> {
-  let Inst{7-6} = 0b00;
+                      (outs DPR:$Dm), (ins GPR:$Rt, GPR:$Rt2),
+                      IIC_fpMOVID, "vmov", "\t$Dm, $Rt, $Rt2",
+                      [(set DPR:$Dm, (arm_fmdrr GPR:$Rt, GPR:$Rt2))]> {
+  // Instruction operands.
+  bits<5> Dm;
+  bits<4> Rt;
+  bits<4> Rt2;
+
+  // Encode instruction operands.
+  let Inst{3-0}   = Dm{3-0};
+  let Inst{5}     = Dm{4};
+  let Inst{15-12} = Rt;
+  let Inst{19-16} = Rt2;
+
+  let Inst{7-6}   = 0b00;
 }
 
 let neverHasSideEffects = 1 in

Modified: llvm/trunk/test/MC/ARM/simple-fp-encoding.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/simple-fp-encoding.ll?rev=116970&r1=116969&r2=116970&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/simple-fp-encoding.ll (original)
+++ llvm/trunk/test/MC/ARM/simple-fp-encoding.ll Wed Oct 20 18:37:40 2010
@@ -423,3 +423,11 @@
 }
 
 declare void @g104(i32, i32, i32, i32, i32, i32)
+
+define double @f105(i32 %a) nounwind readnone {
+entry:
+; CHECK: f105
+; CHECK: vmov r0, r1, d16            @ encoding: [0x30,0x0b,0x51,0xec]
+  %conv = uitofp i32 %a to double
+  ret double %conv
+}