[llvm-commits] [llvm] r116701 - in /llvm/trunk: lib/Target/CellSPU/SPUISelLowering.cpp test/CodeGen/CellSPU/sext128.ll

[Kalle Raiskila]

Author: kraiskil
Date: Mon Oct 18 04:34:19 2010
New Revision: 116701

URL: http://llvm.org/viewvc/llvm-project?rev=116701&view=rev
Log:
Improve lowering of sext to i128 on SPU.
The old algorithm inserted a 'rotqmbyi' instruction which was
both redundant and wrong - it made shufb select bytes from the
wrong end of the input quad.

Modified:
    llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp
    llvm/trunk/test/CodeGen/CellSPU/sext128.ll

Modified: llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp?rev=116701&r1=116700&r2=116701&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp Mon Oct 18 04:34:19 2010
@@ -2642,11 +2642,16 @@
                  DAG.getNode(SPUISD::PREFSLOT2VEC, dl, mvt, Op0, Op0),
                  DAG.getConstant(31, MVT::i32));
 
+  // reinterpret as a i128 (SHUFB requires it). This gets lowered away.
+  SDValue extended = SDValue(DAG.getMachineNode(TargetOpcode::COPY_TO_REGCLASS, 
+                                        dl, Op0VT, Op0,
+                                        DAG.getTargetConstant(
+                                                  SPU::GPRCRegClass.getID(), 
+                                                  MVT::i32)), 0);
   // Shuffle bytes - Copy the sign bits into the upper 64 bits
   // and the input value into the lower 64 bits.
   SDValue extShuffle = DAG.getNode(SPUISD::SHUFB, dl, mvt,
-      DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i128, Op0), sraVal, shufMask);
-
+        extended, sraVal, shufMask);
   return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i128, extShuffle);
 }
 

Modified: llvm/trunk/test/CodeGen/CellSPU/sext128.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CellSPU/sext128.ll?rev=116701&r1=116700&r2=116701&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/CellSPU/sext128.ll (original)
+++ llvm/trunk/test/CodeGen/CellSPU/sext128.ll Mon Oct 18 04:34:19 2010
@@ -12,6 +12,7 @@
 ; CHECK: 	long	269488144
 ; CHECK:	long	66051
 ; CHECK: 	long	67438087
+; CHECK-NOT: rotqmbyi
 ; CHECK: 	rotmai
 ; CHECK:	lqa
 ; CHECK:	shufb
@@ -25,6 +26,7 @@
 ; CHECK: 	long	269488144
 ; CHECK: 	long	269488144
 ; CHECK:	long	66051
+; CHECK-NOT: rotqmbyi
 ; CHECK: 	rotmai
 ; CHECK:	lqa
 ; CHECK:	shufb
@@ -39,6 +41,7 @@
 ; CHECK: 	long	269488144
 ; CHECK: 	long	269488144
 ; CHECK:	long	66051
+; CHECK-NOT: rotqmbyi
 ; CHECK: 	rotmai
 ; CHECK:	lqa
 ; CHECK:	shufb