[llvm-commits] [llvm] r116383 - in /llvm/trunk: lib/Target/ARM/ARMInstrVFP.td test/MC/ARM/simple-fp-encoding.ll
Bill Wendling
isanbard at gmail.com
Tue Oct 12 17:38:07 PDT 2010
Author: void
Date: Tue Oct 12 19:38:07 2010
New Revision: 116383
URL: http://llvm.org/viewvc/llvm-project?rev=116383&view=rev
Log:
Add VCMPZ and VABS.
Modified:
llvm/trunk/lib/Target/ARM/ARMInstrVFP.td
llvm/trunk/test/MC/ARM/simple-fp-encoding.ll
Modified: llvm/trunk/lib/Target/ARM/ARMInstrVFP.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrVFP.td?rev=116383&r1=116382&r2=116383&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrVFP.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Tue Oct 12 19:38:07 2010
@@ -175,27 +175,28 @@
let Inst{22} = Dd{4};
}
-class ASuI_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
- bits<2> opcod4, bit opcod5, dag oops, dag iops,
- InstrItinClass itin, string opc, string asm,
+class ASbI_Encode<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
+ dag iops, InstrItinClass itin, string opc, string asm,
list<dag> pattern>
- : ASuI<opcod1, opcod2, opcod3, opcod4, opcod5, oops, iops, itin, opc,
- asm, pattern> {
+ : ASbI<opcod1, opcod2, op6, op4, oops, iops, itin, opc, asm, pattern> {
// Instruction operands.
bits<5> Sd;
+ bits<5> Sn;
bits<5> Sm;
// Encode instruction operands.
let Inst{3-0} = Sm{4-1};
let Inst{5} = Sm{0};
+ let Inst{19-16} = Sn{4-1};
+ let Inst{7} = Sn{0};
let Inst{15-12} = Sd{4-1};
let Inst{22} = Sd{0};
}
-class ASbI_Encode<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
- dag iops, InstrItinClass itin, string opc, string asm,
- list<dag> pattern>
- : ASbI<opcod1, opcod2, op6, op4, oops, iops, itin, opc, asm, pattern> {
+class ASbIn_Encode<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
+ dag iops, InstrItinClass itin, string opc, string asm,
+ list<dag> pattern>
+ : ASbIn<opcod1, opcod2, op6, op4, oops, iops, itin, opc, asm, pattern> {
// Instruction operands.
bits<5> Sd;
bits<5> Sn;
@@ -210,20 +211,36 @@
let Inst{22} = Sd{0};
}
-class ASbIn_Encode<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
- dag iops, InstrItinClass itin, string opc, string asm,
+class ASuI_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
+ bits<2> opcod4, bit opcod5, dag oops, dag iops,
+ InstrItinClass itin, string opc, string asm,
+ list<dag> pattern>
+ : ASuI<opcod1, opcod2, opcod3, opcod4, opcod5, oops, iops, itin, opc,
+ asm, pattern> {
+ // Instruction operands.
+ bits<5> Sd;
+ bits<5> Sm;
+
+ // Encode instruction operands.
+ let Inst{3-0} = Sm{4-1};
+ let Inst{5} = Sm{0};
+ let Inst{15-12} = Sd{4-1};
+ let Inst{22} = Sd{0};
+}
+
+class ASuIn_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
+ bits<2> opcod4, bit opcod5, dag oops, dag iops,
+ InstrItinClass itin, string opc, string asm,
list<dag> pattern>
- : ASbIn<opcod1, opcod2, op6, op4, oops, iops, itin, opc, asm, pattern> {
+ : ASuIn<opcod1, opcod2, opcod3, opcod4, opcod5, oops, iops, itin, opc,
+ asm, pattern> {
// Instruction operands.
bits<5> Sd;
- bits<5> Sn;
bits<5> Sm;
// Encode instruction operands.
let Inst{3-0} = Sm{4-1};
let Inst{5} = Sm{0};
- let Inst{19-16} = Sn{4-1};
- let Inst{7} = Sn{0};
let Inst{15-12} = Sd{4-1};
let Inst{22} = Sd{0};
}
@@ -313,27 +330,37 @@
// FP Unary Operations.
//
-def VABSD : ADuI<0b11101, 0b11, 0b0000, 0b11, 0, (outs DPR:$dst), (ins DPR:$a),
- IIC_fpUNA64, "vabs", ".f64\t$dst, $a",
- [(set DPR:$dst, (fabs (f64 DPR:$a)))]>;
-
-def VABSS : ASuIn<0b11101, 0b11, 0b0000, 0b11, 0,(outs SPR:$dst), (ins SPR:$a),
- IIC_fpUNA32, "vabs", ".f32\t$dst, $a",
- [(set SPR:$dst, (fabs SPR:$a))]>;
+def VABSD : ADuI_Encode<0b11101, 0b11, 0b0000, 0b11, 0,
+ (outs DPR:$Dd), (ins DPR:$Dm),
+ IIC_fpUNA64, "vabs", ".f64\t$Dd, $Dm",
+ [(set DPR:$Dd, (fabs (f64 DPR:$Dm)))]>;
+
+def VABSS : ASuIn_Encode<0b11101, 0b11, 0b0000, 0b11, 0,
+ (outs SPR:$Sd), (ins SPR:$Sm),
+ IIC_fpUNA32, "vabs", ".f32\t$Sd, $Sm",
+ [(set SPR:$Sd, (fabs SPR:$Sm))]>;
let Defs = [FPSCR] in {
-def VCMPEZD : ADuI<0b11101, 0b11, 0b0101, 0b11, 0, (outs), (ins DPR:$a),
- IIC_fpCMP64, "vcmpe", ".f64\t$a, #0",
- [(arm_cmpfp0 (f64 DPR:$a))]>;
+def VCMPEZD : ADuI_Encode<0b11101, 0b11, 0b0101, 0b11, 0,
+ (outs), (ins DPR:$Dd),
+ IIC_fpCMP64, "vcmpe", ".f64\t$Dd, #0",
+ [(arm_cmpfp0 (f64 DPR:$Dd))]> {
+ let Inst{3-0} = 0b0000;
+ let Inst{5} = 0;
+}
+
+def VCMPEZS : ASuI_Encode<0b11101, 0b11, 0b0101, 0b11, 0,
+ (outs), (ins SPR:$Sd),
+ IIC_fpCMP32, "vcmpe", ".f32\t$Sd, #0",
+ [(arm_cmpfp0 SPR:$Sd)]> {
+ let Inst{3-0} = 0b0000;
+ let Inst{5} = 0;
+}
def VCMPZD : ADuI<0b11101, 0b11, 0b0101, 0b01, 0, (outs), (ins DPR:$a),
IIC_fpCMP64, "vcmp", ".f64\t$a, #0",
[/* For disassembly only; pattern left blank */]>;
-def VCMPEZS : ASuI<0b11101, 0b11, 0b0101, 0b11, 0, (outs), (ins SPR:$a),
- IIC_fpCMP32, "vcmpe", ".f32\t$a, #0",
- [(arm_cmpfp0 SPR:$a)]>;
-
def VCMPZS : ASuI<0b11101, 0b11, 0b0101, 0b01, 0, (outs), (ins SPR:$a),
IIC_fpCMP32, "vcmp", ".f32\t$a, #0",
[/* For disassembly only; pattern left blank */]>;
Modified: llvm/trunk/test/MC/ARM/simple-fp-encoding.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/simple-fp-encoding.ll?rev=116383&r1=116382&r2=116383&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/simple-fp-encoding.ll (original)
+++ llvm/trunk/test/MC/ARM/simple-fp-encoding.ll Tue Oct 12 19:38:07 2010
@@ -104,3 +104,39 @@
%cmp = fcmp oeq float %a, %b
ret i1 %cmp
}
+
+define i1 @f13(double %a) nounwind readnone {
+entry:
+; CHECK: f13
+; CHECK: vcmpe.f64 d16, #0 @ encoding: [0xc0,0x0b,0xf5,0xee]
+ %cmp = fcmp oeq double %a, 0.000000e+00
+ ret i1 %cmp
+}
+
+define i1 @f14(float %a) nounwind readnone {
+entry:
+; CHECK: f14
+; CHECK: vcmpe.f32 s0, #0 @ encoding: [0xc0,0x0a,0xb5,0xee]
+ %cmp = fcmp oeq float %a, 0.000000e+00
+ ret i1 %cmp
+}
+
+define double @f15(double %a) nounwind {
+entry:
+; CHECK: f15
+; CHECK: vabs.f64 d16, d16 @ encoding: [0xe0,0x0b,0xf0,0xee]
+ %call = tail call double @fabsl(double %a)
+ ret double %call
+}
+
+declare double @fabsl(double)
+
+define float @f16(float %a) nounwind {
+entry:
+; CHECK: f16
+; This call generates a "bfc" instruction instead of "vabs.f32".
+ %call = tail call float @fabsf(float %a)
+ ret float %call
+}
+
+declare float @fabsf(float)
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