[llvm-commits] [llvm] r116348 - in /llvm/trunk: lib/Target/ARM/ARMInstrVFP.td test/MC/ARM/simple-fp-encoding.ll

[Jim Grosbach]

Not really. It might make sense to put some of those bits on the same line, though, which would help (the portions that are encoding different pieces of the same operand, e.g.). Something like:

  bits<5> Dd;  bits<5> Dn;  bits<5> Dm;
  let Inst{3-0} = Dm{3-0};  let Inst{5} = Dm{4};
  let Inst{19-16} = Dn{3-0}; let Inst{7} = Dn{4};
  let Inst{15-12} = Dd{3-0}; let Inst{22} = Dd{4};

We may also be able to later refactor some of this sort of thing to put lots of stuff in the base classes rather than the per-instruction patterns. That would help even more. I'm not sure our definitions are laid out in a way that makes that very easy, though (dunno that they're not, either).

-jim

On Oct 12, 2010, at 3:40 PM, Bob Wilson wrote:

> Is there a more concise way to provide this information?  I'm concerned that adding 10 or so lines of operand encodings to all our instruction definitions will make our .td files huge and hard to navigate.
> 
> On Oct 12, 2010, at 3:08 PM, Bill Wendling wrote:
> 
>> Author: void
>> Date: Tue Oct 12 17:08:41 2010
>> New Revision: 116348
>> 
>> URL: http://llvm.org/viewvc/llvm-project?rev=116348&view=rev
>> Log:
>> Encoding for VADDD. Plus a test for the VFP instructions.
>> 
>> Added:
>>   llvm/trunk/test/MC/ARM/simple-fp-encoding.ll
>> Modified:
>>   llvm/trunk/lib/Target/ARM/ARMInstrVFP.td
>> 
>> Modified: llvm/trunk/lib/Target/ARM/ARMInstrVFP.td
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrVFP.td?rev=116348&r1=116347&r2=116348&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/ARM/ARMInstrVFP.td (original)
>> +++ llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Tue Oct 12 17:08:41 2010
>> @@ -142,9 +142,20 @@
>> // FP Binary Operations.
>> //
>> 
>> -def VADDD  : ADbI<0b11100, 0b11, 0, 0, (outs DPR:$dst), (ins DPR:$a, DPR:$b),
>> -                 IIC_fpALU64, "vadd", ".f64\t$dst, $a, $b",
>> -                 [(set DPR:$dst, (fadd DPR:$a, (f64 DPR:$b)))]>;
>> +def VADDD  : ADbI<0b11100, 0b11, 0, 0, (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
>> +                 IIC_fpALU64, "vadd", ".f64\t$Dd, $Dn, $Dm",
>> +                 [(set DPR:$Dd, (fadd DPR:$Dn, (f64 DPR:$Dm)))]> {
>> +  bits<5> Dd;
>> +  bits<5> Dn;
>> +  bits<5> Dm;
>> +
>> +  let Inst{3-0}   = Dm{3-0};
>> +  let Inst{5}     = Dm{4};
>> +  let Inst{19-16} = Dn{3-0};
>> +  let Inst{7}     = Dn{4};
>> +  let Inst{15-12} = Dd{3-0};
>> +  let Inst{22}    = Dd{4};
>> +}
>> 
>> def VADDS  : ASbIn<0b11100, 0b11, 0, 0, (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
>>                  IIC_fpALU32, "vadd", ".f32\t$Sd, $Sn, $Sm",
>> 
>> Added: llvm/trunk/test/MC/ARM/simple-fp-encoding.ll
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/simple-fp-encoding.ll?rev=116348&view=auto
>> ==============================================================================
>> --- llvm/trunk/test/MC/ARM/simple-fp-encoding.ll (added)
>> +++ llvm/trunk/test/MC/ARM/simple-fp-encoding.ll Tue Oct 12 17:08:41 2010
>> @@ -0,0 +1,23 @@
>> +;RUN: llc -mtriple=armv7-apple-darwin -mcpu=cortex-a8 -mattr=-neonfp -show-mc-encoding < %s | FileCheck %s
>> +
>> +
>> +; FIXME: Once the ARM integrated assembler is up and going, these sorts of tests
>> +;        should run on .s source files rather than using llc to generate the
>> +;        assembly.
>> +
>> +
>> +define arm_aapcscc float @f1(float %a, float %b) nounwind {
>> +entry:
>> +; CHECK: f1
>> +; CHECK: vadd.f32 s0, s1, s0  @ encoding: [0x80,0x0a,0x30,0xee]
>> +  %add = fadd float %a, %b
>> +  ret float %add
>> +}
>> +
>> +define arm_aapcscc double @f2(double %a, double %b) nounwind {
>> +entry:
>> +; CHECK: f2
>> +; CHECK: vadd.f64 d16, d17, d16  @ encoding: [0xa0,0x0b,0x71,0xee]
>> +  %add = fadd double %a, %b
>> +  ret double %add
>> +}
>> 
>> 
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