[llvm-commits] [llvm] r116321 - in /llvm/trunk/lib/Target/ARM: ARMInstrInfo.td ARMMCCodeEmitter.cpp

[Jim Grosbach]

Author: grosbach
Date: Tue Oct 12 13:09:12 2010
New Revision: 116321

URL: http://llvm.org/viewvc/llvm-project?rev=116321&view=rev
Log:
Add MOVi ARM encoding.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
    llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=116321&r1=116320&r2=116321&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Tue Oct 12 13:09:12 2010
@@ -1513,40 +1513,43 @@
 //
 
 let neverHasSideEffects = 1 in
-def MOVr : AsI1<0b1101, (outs GPR:$dst), (ins GPR:$src), DPFrm, IIC_iMOVr,
-                "mov", "\t$dst, $src", []>, UnaryDP {
-  bits<4> dst;
-  bits<4> src;
+def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
+                "mov", "\t$Rd, $Rm", []>, UnaryDP {
+  bits<4> Rd;
+  bits<4> Rm;
 
   let Inst{11-4} = 0b00000000;
   let Inst{25} = 0;
-  let Inst{3-0} = src;
-  let Inst{15-12} = dst;
+  let Inst{3-0} = Rm;
+  let Inst{15-12} = Rd;
 }
 
 // A version for the smaller set of tail call registers.
 let neverHasSideEffects = 1 in
-def MOVr_TC : AsI1<0b1101, (outs tcGPR:$dst), (ins tcGPR:$src), DPFrm, 
-                IIC_iMOVr, "mov", "\t$dst, $src", []>, UnaryDP {
-  bits<4> dst;
-  bits<4> src;
+def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm, 
+                IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP {
+  bits<4> Rd;
+  bits<4> Rm;
 
   let Inst{11-4} = 0b00000000;
   let Inst{25} = 0;
-  let Inst{3-0} = src;
-  let Inst{15-12} = dst;
+  let Inst{3-0} = Rm;
+  let Inst{15-12} = Rd;
 }
 
-def MOVs : AsI1<0b1101, (outs GPR:$dst), (ins so_reg:$src),
+def MOVs : AsI1<0b1101, (outs GPR:$Rd), (ins so_reg:$src),
                 DPSoRegFrm, IIC_iMOVsr,
-                "mov", "\t$dst, $src", [(set GPR:$dst, so_reg:$src)]>, UnaryDP {
+                "mov", "\t$Rd, $src", [(set GPR:$Rd, so_reg:$src)]>, UnaryDP {
   let Inst{25} = 0;
 }
 
 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
 def MOVi : AsI1<0b1101, (outs GPR:$dst), (ins so_imm:$src), DPFrm, IIC_iMOVi,
                 "mov", "\t$dst, $src", [(set GPR:$dst, so_imm:$src)]>, UnaryDP {
+  bits<4> Rd;
   let Inst{25} = 1;
+  let Inst{15-12} = Rd;
+  let Inst{19-16} = 0b0000;
 }
 
 let isReMaterializable = 1, isAsCheapAsAMove = 1 in

Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp?rev=116321&r1=116320&r2=116321&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Tue Oct 12 13:09:12 2010
@@ -150,6 +150,13 @@
   unsigned Value = getBinaryCodeForInstr(MI);
   switch (Opcode) {
   default: break;
+  case ARM::MOVi:
+    // The 's' bit.
+    if (MI.getOperand(4).getReg() == ARM::CPSR)
+      Value |= 1 << ARMII::S_BitShift;
+    // The shifted immediate value.
+    Value |= getMachineSoImmOpValue((unsigned)MI.getOperand(1).getImm());
+    break;
   case ARM::ADDri:
   case ARM::ANDri:
   case ARM::BICri: