[llvm-commits] [llvm] r116168 - in /llvm/trunk: lib/Target/PowerPC/PPCISelLowering.cpp test/CodeGen/PowerPC/varargs.ll

[Chris Lattner]

Author: lattner
Date: Sun Oct 10 13:34:00 2010
New Revision: 116168

URL: http://llvm.org/viewvc/llvm-project?rev=116168&view=rev
Log:
fix the expansion of va_arg instruction on PPC to know the arg 
alignment for PPC32/64, avoiding some masking operations.

llvm-gcc expands vaarg inline instead of using the instruction
so it has never hit this.


Added:
    llvm/trunk/test/CodeGen/PowerPC/varargs.ll
Modified:
    llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp

Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=116168&r1=116167&r2=116168&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Sun Oct 10 13:34:00 2010
@@ -73,6 +73,10 @@
   setUseUnderscoreSetJmp(true);
   setUseUnderscoreLongJmp(true);
 
+  // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all
+  // arguments are at least 4/8 bytes aligned.
+  setMinStackArgumentAlignment(TM.getSubtarget<PPCSubtarget>().isPPC64() ? 8:4);
+    
   // Set up the register classes.
   addRegisterClass(MVT::i32, PPC::GPRCRegisterClass);
   addRegisterClass(MVT::f32, PPC::F4RCRegisterClass);

Added: llvm/trunk/test/CodeGen/PowerPC/varargs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/varargs.ll?rev=116168&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/varargs.ll (added)
+++ llvm/trunk/test/CodeGen/PowerPC/varargs.ll Sun Oct 10 13:34:00 2010
@@ -0,0 +1,22 @@
+; RUN: llc < %s -march=ppc32 | FileCheck -check-prefix=P32 %s
+; RUN: llc < %s -march=ppc64 | FileCheck -check-prefix=P64 %s
+
+; PR8327
+define i8* @test1(i8** %foo) nounwind {
+  %A = va_arg i8** %foo, i8*
+  ret i8* %A
+}
+
+; P32: test1:
+; P32: 	lwz r4, 0(r3)
+; P32:	addi r5, r4, 4
+; P32:	stw r5, 0(r3)
+; P32:	lwz r3, 0(r4)
+; P32:	blr 
+
+; P64: test1:
+; P64: ld r4, 0(r3)
+; P64: addi r5, r4, 8
+; P64: std r5, 0(r3)
+; P64: ld r3, 0(r4)
+; P64: blr