[llvm-commits] [llvm] r116140 - in /llvm/trunk/lib/Target/ARM: ARMInstrNEON.td ARMSchedule.td ARMScheduleA8.td ARMScheduleA9.td
Evan Cheng
evan.cheng at apple.com
Fri Oct 8 18:45:34 PDT 2010
Author: evancheng
Date: Fri Oct 8 20:45:34 2010
New Revision: 116140
URL: http://llvm.org/viewvc/llvm-project?rev=116140&view=rev
Log:
Finish vld3 and vld4.
Modified:
llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
llvm/trunk/lib/Target/ARM/ARMSchedule.td
llvm/trunk/lib/Target/ARM/ARMScheduleA8.td
llvm/trunk/lib/Target/ARM/ARMScheduleA9.td
Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=116140&r1=116139&r2=116140&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Fri Oct 8 20:45:34 2010
@@ -344,7 +344,7 @@
class VLD3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
: NLdSt<0, 0b10, op11_8, op7_4,
(outs DPR:$dst1, DPR:$dst2, DPR:$dst3, GPR:$wb),
- (ins addrmode6:$addr, am6offset:$offset), IIC_VLD3,
+ (ins addrmode6:$addr, am6offset:$offset), IIC_VLD3u,
"vld3", Dt, "\\{$dst1, $dst2, $dst3\\}, $addr$offset",
"$addr.addr = $wb", []>;
@@ -352,9 +352,9 @@
def VLD3d16_UPD : VLD3DWB<0b0100, 0b0100, "16">;
def VLD3d32_UPD : VLD3DWB<0b0100, 0b1000, "32">;
-def VLD3d8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3>;
-def VLD3d16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3>;
-def VLD3d32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3>;
+def VLD3d8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
+def VLD3d16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
+def VLD3d32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
// ...with double-spaced registers (non-updating versions for disassembly only):
def VLD3q8 : VLD3D<0b0101, 0b0000, "8">;
@@ -364,14 +364,14 @@
def VLD3q16_UPD : VLD3DWB<0b0101, 0b0100, "16">;
def VLD3q32_UPD : VLD3DWB<0b0101, 0b1000, "32">;
-def VLD3q8Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3>;
-def VLD3q16Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3>;
-def VLD3q32Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3>;
+def VLD3q8Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
+def VLD3q16Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
+def VLD3q32Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
// ...alternate versions to be allocated odd register numbers:
-def VLD3q8oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3>;
-def VLD3q16oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3>;
-def VLD3q32oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3>;
+def VLD3q8oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
+def VLD3q16oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
+def VLD3q32oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
// VLD4 : Vector Load (multiple 4-element structures)
class VLD4D<bits<4> op11_8, bits<4> op7_4, string Dt>
@@ -499,7 +499,7 @@
class VLD3LN<bits<4> op11_8, bits<4> op7_4, string Dt>
: NLdSt<1, 0b10, op11_8, op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3),
(ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
- nohash_imm:$lane), IIC_VLD3, "vld3", Dt,
+ nohash_imm:$lane), IIC_VLD3ln, "vld3", Dt,
"\\{$dst1[$lane], $dst2[$lane], $dst3[$lane]\\}, $addr",
"$src1 = $dst1, $src2 = $dst2, $src3 = $dst3", []>;
@@ -507,16 +507,16 @@
def VLD3LNd16 : VLD3LN<0b0110, {?,?,0,0}, "16">;
def VLD3LNd32 : VLD3LN<0b1010, {?,0,0,0}, "32">;
-def VLD3LNd8Pseudo : VLDQQLNPseudo<IIC_VLD3>;
-def VLD3LNd16Pseudo : VLDQQLNPseudo<IIC_VLD3>;
-def VLD3LNd32Pseudo : VLDQQLNPseudo<IIC_VLD3>;
+def VLD3LNd8Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
+def VLD3LNd16Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
+def VLD3LNd32Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
// ...with double-spaced registers:
def VLD3LNq16 : VLD3LN<0b0110, {?,?,1,0}, "16">;
def VLD3LNq32 : VLD3LN<0b1010, {?,1,0,0}, "32">;
-def VLD3LNq16Pseudo : VLDQQQQLNPseudo<IIC_VLD3>;
-def VLD3LNq32Pseudo : VLDQQQQLNPseudo<IIC_VLD3>;
+def VLD3LNq16Pseudo : VLDQQQQLNPseudo<IIC_VLD3ln>;
+def VLD3LNq32Pseudo : VLDQQQQLNPseudo<IIC_VLD3ln>;
// ...with address register writeback:
class VLD3LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
@@ -524,7 +524,7 @@
(outs DPR:$dst1, DPR:$dst2, DPR:$dst3, GPR:$wb),
(ins addrmode6:$addr, am6offset:$offset,
DPR:$src1, DPR:$src2, DPR:$src3, nohash_imm:$lane),
- IIC_VLD3, "vld3", Dt,
+ IIC_VLD3lnu, "vld3", Dt,
"\\{$dst1[$lane], $dst2[$lane], $dst3[$lane]\\}, $addr$offset",
"$src1 = $dst1, $src2 = $dst2, $src3 = $dst3, $addr.addr = $wb",
[]>;
@@ -533,15 +533,15 @@
def VLD3LNd16_UPD : VLD3LNWB<0b0110, {?,?,0,0}, "16">;
def VLD3LNd32_UPD : VLD3LNWB<0b1010, {?,0,0,0}, "32">;
-def VLD3LNd8Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3>;
-def VLD3LNd16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3>;
-def VLD3LNd32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3>;
+def VLD3LNd8Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
+def VLD3LNd16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
+def VLD3LNd32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
def VLD3LNq16_UPD : VLD3LNWB<0b0110, {?,?,1,0}, "16">;
def VLD3LNq32_UPD : VLD3LNWB<0b1010, {?,1,0,0}, "32">;
-def VLD3LNq16Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD3>;
-def VLD3LNq32Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD3>;
+def VLD3LNq16Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD3lnu>;
+def VLD3LNq32Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD3lnu>;
// VLD4LN : Vector Load (single 4-element structure to one lane)
class VLD4LN<bits<4> op11_8, bits<4> op7_4, string Dt>
Modified: llvm/trunk/lib/Target/ARM/ARMSchedule.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSchedule.td?rev=116140&r1=116139&r2=116140&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMSchedule.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMSchedule.td Fri Oct 8 20:45:34 2010
@@ -141,6 +141,9 @@
def IIC_VLD2ln : InstrItinClass;
def IIC_VLD2lnu : InstrItinClass;
def IIC_VLD3 : InstrItinClass;
+def IIC_VLD3ln : InstrItinClass;
+def IIC_VLD3u : InstrItinClass;
+def IIC_VLD3lnu : InstrItinClass;
def IIC_VLD4 : InstrItinClass;
def IIC_VST : InstrItinClass;
def IIC_VUNAD : InstrItinClass;
Modified: llvm/trunk/lib/Target/ARM/ARMScheduleA8.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMScheduleA8.td?rev=116140&r1=116139&r2=116140&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMScheduleA8.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMScheduleA8.td Fri Oct 8 20:45:34 2010
@@ -441,39 +441,58 @@
[2, 2, 1]>,
//
// VLD2x2
- InstrItinData<IIC_VLD2, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
+ InstrItinData<IIC_VLD2x2, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
InstrStage<3, [A8_NLSPipe], 1>,
InstrStage<3, [A8_LSPipe]>],
[2, 2, 3, 3, 1]>,
//
// VLD2ln
- InstrItinData<IIC_VLD2, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
+ InstrItinData<IIC_VLD2ln, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
InstrStage<3, [A8_NLSPipe], 1>,
InstrStage<3, [A8_LSPipe]>],
[3, 3, 1, 1, 1, 1]>,
//
// VLD2u
- InstrItinData<IIC_VLD2, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
+ InstrItinData<IIC_VLD2u, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
InstrStage<1, [A8_NLSPipe], 1>,
InstrStage<1, [A8_LSPipe]>],
[2, 2, 2, 1, 1, 1]>,
//
// VLD2x2u
- InstrItinData<IIC_VLD2, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
+ InstrItinData<IIC_VLD2x2u, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
InstrStage<3, [A8_NLSPipe], 1>,
InstrStage<3, [A8_LSPipe]>],
[2, 2, 3, 3, 2, 1]>,
//
// VLD2lnu
- InstrItinData<IIC_VLD2, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
+ InstrItinData<IIC_VLD2lnu, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
InstrStage<3, [A8_NLSPipe], 1>,
InstrStage<3, [A8_LSPipe]>],
[3, 3, 2, 1, 1, 1, 1, 1]>,
//
// VLD3
InstrItinData<IIC_VLD3, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
- InstrStage<1, [A8_NLSPipe]>,
- InstrStage<1, [A8_LSPipe]>], [2, 2, 2, 1]>,
+ InstrStage<4, [A8_NLSPipe], 1>,
+ InstrStage<4, [A8_LSPipe]>],
+ [3, 3, 4, 1]>,
+ //
+ // VLD3ln
+ InstrItinData<IIC_VLD3ln, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
+ InstrStage<5, [A8_NLSPipe], 1>,
+ InstrStage<5, [A8_LSPipe]>],
+ [4, 4, 5, 1, 1, 1, 1, 2]>,
+ //
+ // VLD3u
+ InstrItinData<IIC_VLD3u, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
+ InstrStage<4, [A8_NLSPipe], 1>,
+ InstrStage<4, [A8_LSPipe]>],
+ [3, 3, 4, 2, 1]>,
+ //
+ // VLD3lnu
+ InstrItinData<IIC_VLD3lnu, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
+ InstrStage<5, [A8_NLSPipe], 1>,
+ InstrStage<5, [A8_LSPipe]>],
+ [4, 4, 5, 2, 1, 1, 1, 1, 1, 2]>,
//
// VLD4
InstrItinData<IIC_VLD4, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
Modified: llvm/trunk/lib/Target/ARM/ARMScheduleA9.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMScheduleA9.td?rev=116140&r1=116139&r2=116140&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMScheduleA9.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMScheduleA9.td Fri Oct 8 20:45:34 2010
@@ -822,14 +822,36 @@
[4, 4, 2, 1, 1, 1, 1, 1]>,
//
// VLD3
- // FIXME: We don't model this instruction properly
InstrItinData<IIC_VLD3, [InstrStage<1, [A9_DRegsN], 0, Required>,
- // Extra latency cycles since wbck is 6 cycles
- InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
+ InstrStage<10, [A9_DRegsVFP], 0, Reserved>,
InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
InstrStage<1, [A9_MUX0], 0>,
- InstrStage<1, [A9_NPipe]>],
- [2, 2, 2, 1]>,
+ InstrStage<4, [A9_NPipe]>],
+ [4, 4, 5, 1]>,
+ //
+ // VLD3ln
+ InstrItinData<IIC_VLD3ln, [InstrStage<1, [A9_DRegsN], 0, Required>,
+ InstrStage<11, [A9_DRegsVFP], 0, Reserved>,
+ InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
+ InstrStage<1, [A9_MUX0], 0>,
+ InstrStage<5, [A9_NPipe]>],
+ [5, 5, 6, 1, 1, 1, 1, 2]>,
+ //
+ // VLD3u
+ InstrItinData<IIC_VLD3u, [InstrStage<1, [A9_DRegsN], 0, Required>,
+ InstrStage<10, [A9_DRegsVFP], 0, Reserved>,
+ InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
+ InstrStage<1, [A9_MUX0], 0>,
+ InstrStage<4, [A9_NPipe]>],
+ [4, 4, 5, 2, 1]>,
+ //
+ // VLD3lnu
+ InstrItinData<IIC_VLD3lnu, [InstrStage<1, [A9_DRegsN], 0, Required>,
+ InstrStage<11, [A9_DRegsVFP], 0, Reserved>,
+ InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
+ InstrStage<1, [A9_MUX0], 0>,
+ InstrStage<5, [A9_NPipe]>],
+ [5, 5, 6, 2, 1, 1, 1, 1, 1, 2]>,
//
// VLD4
// FIXME: We don't model this instruction properly
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