[llvm-commits] [llvm] r115987 - /llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp

[Jim Grosbach]

Author: grosbach
Date: Thu Oct  7 16:57:55 2010
New Revision: 115987

URL: http://llvm.org/viewvc/llvm-project?rev=115987&view=rev
Log:
Include the auto-generated bits for machine encoding.

Modified:
    llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp?rev=115987&r1=115986&r2=115987&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Thu Oct  7 16:57:55 2010
@@ -36,6 +36,17 @@
 
   ~ARMMCCodeEmitter() {}
 
+  // getBinaryCodeForInstr - TableGen'erated function for getting the
+  // binary encoding for an instruction.
+  unsigned getBinaryCodeForInstr(const MCInst &MI);
+
+  /// getMachineOpValue - Return binary encoding of operand. If the machine
+  /// operand requires relocation, record the relocation and return zero.
+  unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO);
+  unsigned getMachineOpValue(const MCInst &MI, unsigned OpIdx) {
+    return getMachineOpValue(MI, MI.getOperand(OpIdx));
+  }
+
   unsigned getNumFixupKinds() const {
     assert(0 && "ARMMCCodeEmitter::getNumFixupKinds() not yet implemented.");
     return 0;
@@ -98,3 +109,12 @@
                   SmallVectorImpl<MCFixup> &Fixups) const {
   assert(0 && "ARMMCCodeEmitter::EncodeInstruction() not yet implemented.");
 }
+
+// FIXME: These #defines shouldn't be necessary. Instead, tblgen should
+// be able to generate code emitter helpers for either variant, like it
+// does for the AsmWriter.
+#define ARMCodeEmitter ARMMCCodeEmitter
+#define MachineInstr MCInst
+#include "ARMGenCodeEmitter.inc"
+#undef ARMCodeEmitter
+#undef MachineInstr