[llvm-commits] [llvm] r115907 - /llvm/trunk/lib/Target/ARM/ARMFastISel.cpp
Eric Christopher
echristo at apple.com
Wed Oct 6 22:50:44 PDT 2010
Author: echristo
Date: Thu Oct 7 00:50:44 2010
New Revision: 115907
URL: http://llvm.org/viewvc/llvm-project?rev=115907&view=rev
Log:
Use the correct register class for load instructions - fixes
compilation of MultiSource/Benchmarks/Bullet.
Modified:
llvm/trunk/lib/Target/ARM/ARMFastISel.cpp
Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=115907&r1=115906&r2=115907&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Thu Oct 7 00:50:44 2010
@@ -652,33 +652,40 @@
assert(VT.isSimple() && "Non-simple types are invalid here!");
unsigned Opc;
+ TargetRegisterClass *RC;
bool isFloat = false;
switch (VT.getSimpleVT().SimpleTy) {
default:
// This is mostly going to be Neon/vector support.
return false;
+ // Using thumb1 instructions for now, use the appropriate RC.
case MVT::i16:
Opc = isThumb ? ARM::tLDRH : ARM::LDRH;
+ RC = isThumb ? ARM::tGPRRegisterClass : ARM::GPRRegisterClass;
VT = MVT::i32;
break;
case MVT::i8:
Opc = isThumb ? ARM::tLDRB : ARM::LDRB;
+ RC = isThumb ? ARM::tGPRRegisterClass : ARM::GPRRegisterClass;
VT = MVT::i32;
break;
case MVT::i32:
Opc = isThumb ? ARM::tLDR : ARM::LDR;
+ RC = isThumb ? ARM::tGPRRegisterClass : ARM::GPRRegisterClass;
break;
case MVT::f32:
Opc = ARM::VLDRS;
+ RC = TLI.getRegClassFor(VT);
isFloat = true;
break;
case MVT::f64:
Opc = ARM::VLDRD;
+ RC = TLI.getRegClassFor(VT);
isFloat = true;
break;
}
- ResultReg = createResultReg(TLI.getRegClassFor(VT));
+ ResultReg = createResultReg(RC);
// TODO: Fix the Addressing modes so that these can share some code.
// Since this is a Thumb1 load this will work in Thumb1 or 2 mode.
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