[llvm-commits] [llvm] r115400 - /llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.cpp

[Evan Cheng]

Thanks Bob.

Evan
On Oct 1, 2010, at 6:49 PM, Bob Wilson wrote:

> Author: bwilson
> Date: Fri Oct  1 20:49:29 2010
> New Revision: 115400
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=115400&view=rev
> Log:
> Fix a miscompile in 186.crafty for Thumb2 that was exposed by Evan's
> scheduling change in svn 115121.  The CriticalAntiDepBreaker had bad
> liveness information.  It was calculating the KillIndices for one scheduling
> region in a basic block, rescheduling that region so the KillIndices were
> no longer valid, and then using those wrong KillIndices to make decisions
> for the next scheduling region.  I've not been able to reduce a small
> testcase for this.  Radar 8502534.
> 
> Modified:
>    llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.cpp
> 
> Modified: llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.cpp?rev=115400&r1=115399&r2=115400&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.cpp (original)
> +++ llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.cpp Fri Oct  1 20:49:29 2010
> @@ -130,21 +130,25 @@
>     return;
>   assert(Count < InsertPosIndex && "Instruction index out of expected range!");
> 
> -  // Any register which was defined within the previous scheduling region
> -  // may have been rescheduled and its lifetime may overlap with registers
> -  // in ways not reflected in our current liveness state. For each such
> -  // register, adjust the liveness state to be conservatively correct.
> -  for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg)
> -    if (DefIndices[Reg] < InsertPosIndex && DefIndices[Reg] >= Count) {
> -      assert(KillIndices[Reg] == ~0u && "Clobbered register is live!");
> -
> -      // Mark this register to be non-renamable.
> +  for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg) {
> +    if (KillIndices[Reg] != ~0u) {
> +      // If Reg is currently live, then mark that it can't be renamed as
> +      // we don't know the extent of its live-range anymore (now that it
> +      // has been scheduled).
> +      Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
> +      KillIndices[Reg] = Count;
> +    } else if (DefIndices[Reg] < InsertPosIndex && DefIndices[Reg] >= Count) {
> +      // Any register which was defined within the previous scheduling region
> +      // may have been rescheduled and its lifetime may overlap with registers
> +      // in ways not reflected in our current liveness state. For each such
> +      // register, adjust the liveness state to be conservatively correct.
>       Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
> 
>       // Move the def index to the end of the previous region, to reflect
>       // that the def could theoretically have been scheduled at the end.
>       DefIndices[Reg] = InsertPosIndex;
>     }
> +  }
> 
>   PrescanInstruction(MI);
>   ScanInstruction(MI, Count);
> @@ -580,7 +584,7 @@
>         }
> 
>         // We just went back in time and modified history; the
> -        // liveness information for the anti-depenence reg is now
> +        // liveness information for the anti-dependence reg is now
>         // inconsistent. Set the state as if it were dead.
>         Classes[NewReg] = Classes[AntiDepReg];
>         DefIndices[NewReg] = DefIndices[AntiDepReg];
> 
> 
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