[llvm-commits] [llvm] r115353 - in /llvm/trunk/lib/Target/ARM: ARMScheduleA8.td ARMScheduleA9.td

[Evan Cheng]

Author: evancheng
Date: Fri Oct  1 16:40:30 2010
New Revision: 115353

URL: http://llvm.org/viewvc/llvm-project?rev=115353&view=rev
Log:
Add operand cycles for vldr / vstr.

Modified:
    llvm/trunk/lib/Target/ARM/ARMScheduleA8.td
    llvm/trunk/lib/Target/ARM/ARMScheduleA9.td

Modified: llvm/trunk/lib/Target/ARM/ARMScheduleA8.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMScheduleA8.td?rev=115353&r1=115352&r2=115353&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMScheduleA8.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMScheduleA8.td Fri Oct  1 16:40:30 2010
@@ -384,7 +384,8 @@
   InstrItinData<IIC_fpLoad32, [InstrStage<1, [A8_Issue], 0>,
                                InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
                                InstrStage<1, [A8_LdSt0], 0>,
-                               InstrStage<1, [A8_NLSPipe]>]>,
+                               InstrStage<1, [A8_NLSPipe]>],
+                              [2, 1]>,
   //
   // Double-precision FP Load
   // use A8_Issue to enforce the 1 load/store per cycle limit
@@ -393,7 +394,8 @@
                                InstrStage<1, [A8_Pipe1]>,
                                InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
                                InstrStage<1, [A8_LdSt0], 0>,
-                               InstrStage<1, [A8_NLSPipe]>]>,
+                               InstrStage<1, [A8_NLSPipe]>],
+                              [2, 1]>,
   //
   // FP Load Multiple
   // use A8_Issue to enforce the 1 load/store per cycle limit
@@ -409,7 +411,8 @@
   InstrItinData<IIC_fpStore32,[InstrStage<1, [A8_Issue], 0>,
                                InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
                                InstrStage<1, [A8_LdSt0], 0>,
-                               InstrStage<1, [A8_NLSPipe]>]>,
+                               InstrStage<1, [A8_NLSPipe]>],
+                              [1, 1]>,
   //
   // Double-precision FP Store
   // use A8_Issue to enforce the 1 load/store per cycle limit
@@ -418,7 +421,8 @@
                                InstrStage<1, [A8_Pipe1]>,
                                InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
                                InstrStage<1, [A8_LdSt0], 0>,
-                               InstrStage<1, [A8_NLSPipe]>]>,
+                               InstrStage<1, [A8_NLSPipe]>],
+                              [1, 1]>,
   //
   // FP Store Multiple
   // use A8_Issue to enforce the 1 load/store per cycle limit

Modified: llvm/trunk/lib/Target/ARM/ARMScheduleA9.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMScheduleA9.td?rev=115353&r1=115352&r2=115353&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMScheduleA9.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMScheduleA9.td Fri Oct  1 16:40:30 2010
@@ -482,13 +482,16 @@
   InstrItinData<IIC_fpLoad32, [InstrStage<1, [A9_DRegsVFP], 0, Required>,
                                InstrStage<2, [A9_DRegsN],   0, Reserved>,
                                InstrStage<1, [A9_Pipe1], 0>,
-                               InstrStage<1, [A9_MUX0, A9_NPipe]>]>,
+                               InstrStage<1, [A9_MUX0, A9_NPipe]>],
+                              [1, 1]>,
   //
   // Double-precision FP Load
+  // FIXME: Result latency is 1 if address is 64-bit aligned.
   InstrItinData<IIC_fpLoad64, [InstrStage<1, [A9_DRegsVFP], 0, Required>,
                                InstrStage<2, [A9_DRegsN],   0, Reserved>,
                                InstrStage<1, [A9_Pipe1], 0>,
-                               InstrStage<1, [A9_MUX0, A9_NPipe]>]>,
+                               InstrStage<1, [A9_MUX0, A9_NPipe]>],
+                              [2, 1]>,
   //
   // FP Load Multiple
   InstrItinData<IIC_fpLoadm,  [InstrStage<1, [A9_DRegsVFP], 0, Required>,
@@ -500,13 +503,15 @@
   InstrItinData<IIC_fpStore32,[InstrStage<1, [A9_DRegsVFP], 0, Required>,
                                InstrStage<2, [A9_DRegsN],   0, Reserved>,
                                InstrStage<1, [A9_Pipe1], 0>,
-                               InstrStage<1, [A9_MUX0, A9_NPipe]>]>,
+                               InstrStage<1, [A9_MUX0, A9_NPipe]>],
+                              [1, 1]>,
   //
   // Double-precision FP Store
   InstrItinData<IIC_fpStore64,[InstrStage<1, [A9_DRegsVFP], 0, Required>,
                                InstrStage<2, [A9_DRegsN],   0, Reserved>,
                                InstrStage<1, [A9_Pipe1], 0>,
-                               InstrStage<1, [A9_MUX0, A9_NPipe]>]>,
+                               InstrStage<1, [A9_MUX0, A9_NPipe]>],
+                              [1, 1]>,
   //
   // FP Store Multiple
   InstrItinData<IIC_fpStorem, [InstrStage<1, [A9_DRegsVFP], 0, Required>,