[llvm-commits] [llvm] r115098 - in /llvm/trunk: include/llvm/Target/TargetInstrItineraries.h lib/CodeGen/ScheduleDAGInstrs.cpp lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp lib/Target/ARM/ARMInstrThumb2.td lib/Target/ARM/ARMSchedule.td lib/Targ

[Evan Cheng]

On Sep 29, 2010, at 3:56 PM, Anton Korobeynikov wrote:

> Hi Evan,
> 
>> Model Cortex-a9 load to SUB, RSB, ADD, ADC, SBC, RSC, CMN, MVN, or CMP
>> pipeline forwarding path.
> Right now the scheduling documentation is pretty sparse...
> Will it be possible to add some hunk of documentation into e.g. .td?

I'm not sure what to write yet. But yes.

> 
> Am I right to understand that currently bypasses always have zero latencies?

No, it reduces the corresponding operand latency by one. It's probably not right, but that fits with the architectures that I am familiar with.

Evan

> 
> -- 
> With best regards, Anton Korobeynikov
> Faculty of Mathematics and Mechanics, Saint Petersburg State University