[llvm-commits] [llvm] r114915 - /llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp

[Jim Grosbach]

Gack. Butterfingered "enter" before getting the commit message edited. That should be "Add Thumb mode MC lowering for eh.sjlj.longjmp". Sorry 'bout that."

On Sep 27, 2010, at 3:28 PM, Jim Grosbach wrote:

> Author: grosbach
> Date: Mon Sep 27 17:28:11 2010
> New Revision: 114915
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=114915&view=rev
> Log:
> Enable the MC-ized ARM asm printer. Passing all local tests, so it's time to
> enable it for real. Leaving the CL option in place to it's easy to disable it
> again if (when) testers find something I've missed.
> 
> Modified:
>    llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
> 
> Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=114915&r1=114914&r2=114915&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Mon Sep 27 17:28:11 2010
> @@ -1974,6 +1974,73 @@
>     }
>     return;
>   }
> +  case ARM::tInt_eh_sjlj_longjmp: {
> +    // ldr $scratch, [$src, #8]
> +    // mov sp, $scratch
> +    // ldr $scratch, [$src, #4]
> +    // ldr r7, [$src]
> +    // bx $scratch
> +    unsigned SrcReg = MI->getOperand(0).getReg();
> +    unsigned ScratchReg = MI->getOperand(1).getReg();
> +    {
> +      MCInst TmpInst;
> +      TmpInst.setOpcode(ARM::tLDR);
> +      TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
> +      TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
> +      // The offset immediate is #8. The operand value is scaled by 4 for the
> +      // tSTR instruction.
> +      TmpInst.addOperand(MCOperand::CreateImm(2));
> +      TmpInst.addOperand(MCOperand::CreateReg(0));
> +      // Predicate.
> +      TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
> +      TmpInst.addOperand(MCOperand::CreateReg(0));
> +      OutStreamer.EmitInstruction(TmpInst);
> +    }
> +    {
> +      MCInst TmpInst;
> +      TmpInst.setOpcode(ARM::tMOVtgpr2gpr);
> +      TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
> +      TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
> +      // Predicate.
> +      TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
> +      TmpInst.addOperand(MCOperand::CreateReg(0));
> +      OutStreamer.EmitInstruction(TmpInst);
> +    }
> +    {
> +      MCInst TmpInst;
> +      TmpInst.setOpcode(ARM::tLDR);
> +      TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
> +      TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
> +      TmpInst.addOperand(MCOperand::CreateImm(1));
> +      TmpInst.addOperand(MCOperand::CreateReg(0));
> +      // Predicate.
> +      TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
> +      TmpInst.addOperand(MCOperand::CreateReg(0));
> +      OutStreamer.EmitInstruction(TmpInst);
> +    }
> +    {
> +      MCInst TmpInst;
> +      TmpInst.setOpcode(ARM::tLDR);
> +      TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
> +      TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
> +      TmpInst.addOperand(MCOperand::CreateImm(0));
> +      TmpInst.addOperand(MCOperand::CreateReg(0));
> +      // Predicate.
> +      TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
> +      TmpInst.addOperand(MCOperand::CreateReg(0));
> +      OutStreamer.EmitInstruction(TmpInst);
> +    }
> +    {
> +      MCInst TmpInst;
> +      TmpInst.setOpcode(ARM::tBX_RET_vararg);
> +      TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
> +      // Predicate.
> +      TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
> +      TmpInst.addOperand(MCOperand::CreateReg(0));
> +      OutStreamer.EmitInstruction(TmpInst);
> +    }
> +    return;
> +  }
>   }
> 
>   MCInst TmpInst;
> 
> 
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