[llvm-commits] [llvm] r114710 - in /llvm/trunk: include/llvm/Target/Target.td include/llvm/Target/TargetInstrDesc.h lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/ARMInstrThumb.td lib/Target/ARM/ARMInstrThumb2.td lib/Target/X86/X86Instr64bit.td lib/Target/X86/X86InstrInfo.td utils/TableGen/CodeGenInstruction.cpp utils/TableGen/CodeGenInstruction.h utils/TableGen/InstrInfoEmitter.cpp
Owen Anderson
resistor at mac.com
Thu Sep 23 16:45:25 PDT 2010
Author: resistor
Date: Thu Sep 23 18:45:25 2010
New Revision: 114710
URL: http://llvm.org/viewvc/llvm-project?rev=114710&view=rev
Log:
Revert r114703 and r114702, removing the isConditionalMove flag from instructions. After further
reflection, this isn't going to achieve the purpose I intended it for. Back to the drawing board!
Modified:
llvm/trunk/include/llvm/Target/Target.td
llvm/trunk/include/llvm/Target/TargetInstrDesc.h
llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
llvm/trunk/lib/Target/X86/X86Instr64bit.td
llvm/trunk/lib/Target/X86/X86InstrInfo.td
llvm/trunk/utils/TableGen/CodeGenInstruction.cpp
llvm/trunk/utils/TableGen/CodeGenInstruction.h
llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp
Modified: llvm/trunk/include/llvm/Target/Target.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/Target.td?rev=114710&r1=114709&r2=114710&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/Target.td (original)
+++ llvm/trunk/include/llvm/Target/Target.td Thu Sep 23 18:45:25 2010
@@ -201,7 +201,6 @@
bit isCompare = 0; // Is this instruction a comparison instruction?
bit isBarrier = 0; // Can control flow fall through this instruction?
bit isCall = 0; // Is this instruction a call instruction?
- bit isConditionalMove = 0; // Is this instruction a conditional move instr?
bit canFoldAsLoad = 0; // Can this be folded as a simple memory operand?
bit mayLoad = 0; // Is it possible for this inst to read memory?
bit mayStore = 0; // Is it possible for this inst to write memory?
Modified: llvm/trunk/include/llvm/Target/TargetInstrDesc.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetInstrDesc.h?rev=114710&r1=114709&r2=114710&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetInstrDesc.h (original)
+++ llvm/trunk/include/llvm/Target/TargetInstrDesc.h Thu Sep 23 18:45:25 2010
@@ -99,7 +99,6 @@
HasOptionalDef,
Return,
Call,
- ConditionalMove,
Barrier,
Terminator,
Branch,
@@ -353,12 +352,6 @@
return Flags & (1 << TID::Compare);
}
- /// isConditionalMove - Return true if this instruction can be considered a
- /// conditional move, like CMOV on X86 or MOVCC on ARM.
- bool isConditionalMove() const {
- return Flags & (1 << TID::ConditionalMove);
- }
-
/// isNotDuplicable - Return true if this instruction cannot be safely
/// duplicated. For example, if the instruction has a unique labels attached
/// to it, duplicating it would cause multiple definition errors.
Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=114710&r1=114709&r2=114710&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Thu Sep 23 18:45:25 2010
@@ -2391,7 +2391,7 @@
// Conditional moves
// FIXME: should be able to write a pattern for ARMcmov, but can't use
// a two-value operand where a dag node expects two operands. :(
-let neverHasSideEffects = 1, isConditionalMove = 1 in {
+let neverHasSideEffects = 1 in {
def MOVCCr : AI1<0b1101, (outs GPR:$dst), (ins GPR:$false, GPR:$true), DPFrm,
IIC_iCMOVr, "mov", "\t$dst, $true",
[/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>,
@@ -2415,7 +2415,7 @@
RegConstraint<"$false = $dst">, UnaryDP {
let Inst{25} = 1;
}
-} // neverHasSideEffects, isConditionalMove
+} // neverHasSideEffects
//===----------------------------------------------------------------------===//
// Atomic operations intrinsics
Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=114710&r1=114709&r2=114710&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Thu Sep 23 18:45:25 2010
@@ -866,7 +866,7 @@
// 16-bit movcc in IT blocks for Thumb2.
-let neverHasSideEffects = 1, isConditionalMove = 1 in {
+let neverHasSideEffects = 1 in {
def tMOVCCr : T1pIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iCMOVr,
"mov", "\t$dst, $rhs", []>,
T1Special<{1,0,?,?}>;
@@ -874,7 +874,7 @@
def tMOVCCi : T1pIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iCMOVi,
"mov", "\t$dst, $rhs", []>,
T1General<{1,0,0,?,?}>;
-} // neverHasSideEffects, isConditionalMove
+} // neverHasSideEffects
// tLEApcrel - Load a pc-relative address into a register without offending the
// assembler.
Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=114710&r1=114709&r2=114710&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Thu Sep 23 18:45:25 2010
@@ -2169,7 +2169,7 @@
// Conditional moves
// FIXME: should be able to write a pattern for ARMcmov, but can't use
// a two-value operand where a dag node expects two operands. :(
-let neverHasSideEffects = 1, isConditionalMove = 1 in {
+let neverHasSideEffects = 1 in {
def t2MOVCCr : T2I<(outs rGPR:$dst), (ins rGPR:$false, rGPR:$true), IIC_iCMOVr,
"mov", ".w\t$dst, $true",
[/*(set rGPR:$dst, (ARMcmov rGPR:$false, rGPR:$true, imm:$cc, CCR:$ccr))*/]>,
@@ -2221,7 +2221,7 @@
(ins rGPR:$false, rGPR:$true, i32imm:$rhs),
IIC_iCMOVsi, "ror", ".w\t$dst, $true, $rhs", []>,
RegConstraint<"$false = $dst">;
-} // neverHasSideEffects, isConditionalMove
+} // neverHasSideEffects
//===----------------------------------------------------------------------===//
// Atomic operations intrinsics
Modified: llvm/trunk/lib/Target/X86/X86Instr64bit.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Instr64bit.td?rev=114710&r1=114709&r2=114710&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86Instr64bit.td (original)
+++ llvm/trunk/lib/Target/X86/X86Instr64bit.td Thu Sep 23 18:45:25 2010
@@ -1366,7 +1366,7 @@
} // Defs = [EFLAGS]
// Conditional moves
-let isConditionalMove = 1, Uses = [EFLAGS], Constraints = "$src1 = $dst" in {
+let Uses = [EFLAGS], Constraints = "$src1 = $dst" in {
let isCommutable = 1 in {
def CMOVB64rr : RI<0x42, MRMSrcReg, // if <u, GR64 = GR64
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
@@ -1530,7 +1530,7 @@
"cmovno{q}\t{$src2, $dst|$dst, $src2}",
[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
X86_COND_NO, EFLAGS))]>, TB;
-} // isConditionalMove, Constraints = "$src1 = $dst"
+} // Constraints = "$src1 = $dst"
// Use sbb to materialize carry flag into a GPR.
// FIXME: This are pseudo ops that should be replaced with Pat<> patterns.
Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=114710&r1=114709&r2=114710&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Thu Sep 23 18:45:25 2010
@@ -1269,7 +1269,7 @@
// Conditional moves
let Uses = [EFLAGS] in {
-let isConditionalMove = 1, Predicates = [HasCMov] in {
+let Predicates = [HasCMov] in {
let isCommutable = 1 in {
def CMOVB16rr : I<0x42, MRMSrcReg, // if <u, GR16 = GR16
(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
@@ -1657,7 +1657,7 @@
[(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
X86_COND_NO, EFLAGS))]>,
TB;
-} // isConditionalMove, Predicates = [HasCMov]
+} // Predicates = [HasCMov]
// X86 doesn't have 8-bit conditional moves. Use a customInserter to
// emit control flow. An alternative to this is to mark i8 SELECT as Promote,
Modified: llvm/trunk/utils/TableGen/CodeGenInstruction.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenInstruction.cpp?rev=114710&r1=114709&r2=114710&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/CodeGenInstruction.cpp (original)
+++ llvm/trunk/utils/TableGen/CodeGenInstruction.cpp Thu Sep 23 18:45:25 2010
@@ -103,7 +103,6 @@
isBranch = R->getValueAsBit("isBranch");
isIndirectBranch = R->getValueAsBit("isIndirectBranch");
isCompare = R->getValueAsBit("isCompare");
- isConditionalMove = R->getValueAsBit("isConditionalMove");
isBarrier = R->getValueAsBit("isBarrier");
isCall = R->getValueAsBit("isCall");
canFoldAsLoad = R->getValueAsBit("canFoldAsLoad");
Modified: llvm/trunk/utils/TableGen/CodeGenInstruction.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenInstruction.h?rev=114710&r1=114709&r2=114710&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/CodeGenInstruction.h (original)
+++ llvm/trunk/utils/TableGen/CodeGenInstruction.h Thu Sep 23 18:45:25 2010
@@ -124,7 +124,6 @@
bool isBranch;
bool isIndirectBranch;
bool isCompare;
- bool isConditionalMove;
bool isBarrier;
bool isCall;
bool canFoldAsLoad;
Modified: llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp?rev=114710&r1=114709&r2=114710&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp Thu Sep 23 18:45:25 2010
@@ -274,7 +274,6 @@
if (Inst.isBarrier) OS << "|(1<<TID::Barrier)";
if (Inst.hasDelaySlot) OS << "|(1<<TID::DelaySlot)";
if (Inst.isCall) OS << "|(1<<TID::Call)";
- if (Inst.isConditionalMove) OS << "|(1<<TID::ConditionalMove)";
if (Inst.canFoldAsLoad) OS << "|(1<<TID::FoldableAsLoad)";
if (Inst.mayLoad) OS << "|(1<<TID::MayLoad)";
if (Inst.mayStore) OS << "|(1<<TID::MayStore)";
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