[llvm-commits] [llvm] r114599 - in /llvm/trunk: lib/CodeGen/SelectionDAG/DAGCombiner.cpp test/CodeGen/X86/bit-test-shift.ll

[Duncan Sands]

Hi Owen,

> A select between a constant and zero, when fed by a bit test, can be efficiently
> lowered using a series of shifts.
> Fixes<rdar://problem/8285015>.

can't you do this at the IR level?  At the IR level, you can change

   %s = select i1 %cond, i32 %a, i32 0

into

   %cond.1 = sext i1 %cond to i32
   %s = and i32 %a, %cond.1

which could be a win depending on where %cond comes from.

Ciao,

Duncan.