[llvm-commits] [llvm] r114445 - /llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
Jim Grosbach
grosbach at apple.com
Tue Sep 21 09:45:31 PDT 2010
Author: grosbach
Date: Tue Sep 21 11:45:31 2010
New Revision: 114445
URL: http://llvm.org/viewvc/llvm-project?rev=114445&view=rev
Log:
Fix errant printing of [v]ldm instructions that aren't a pop
Modified:
llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=114445&r1=114444&r2=114445&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Tue Sep 21 11:45:31 2010
@@ -1174,47 +1174,39 @@
} else
// A8.6.123 PUSH
if ((MI->getOpcode() == ARM::STM_UPD || MI->getOpcode() == ARM::t2STM_UPD) &&
- MI->getOperand(0).getReg() == ARM::SP) {
- const MachineOperand &MO1 = MI->getOperand(2);
- if (ARM_AM::getAM4SubMode(MO1.getImm()) == ARM_AM::db) {
- OS << '\t' << "push";
- printPredicateOperand(MI, 3, OS);
- OS << '\t';
- printRegisterList(MI, 5, OS);
- }
+ MI->getOperand(0).getReg() == ARM::SP &&
+ ARM_AM::getAM4SubMode(MI->getOperand(2).getImm()) == ARM_AM::db) {
+ OS << '\t' << "push";
+ printPredicateOperand(MI, 3, OS);
+ OS << '\t';
+ printRegisterList(MI, 5, OS);
} else
// A8.6.122 POP
if ((MI->getOpcode() == ARM::LDM_UPD || MI->getOpcode() == ARM::t2LDM_UPD) &&
- MI->getOperand(0).getReg() == ARM::SP) {
- const MachineOperand &MO1 = MI->getOperand(2);
- if (ARM_AM::getAM4SubMode(MO1.getImm()) == ARM_AM::ia) {
- OS << '\t' << "pop";
- printPredicateOperand(MI, 3, OS);
- OS << '\t';
- printRegisterList(MI, 5, OS);
- }
+ MI->getOperand(0).getReg() == ARM::SP &&
+ ARM_AM::getAM4SubMode(MI->getOperand(2).getImm()) == ARM_AM::ia) {
+ OS << '\t' << "pop";
+ printPredicateOperand(MI, 3, OS);
+ OS << '\t';
+ printRegisterList(MI, 5, OS);
} else
// A8.6.355 VPUSH
if ((MI->getOpcode() == ARM::VSTMS_UPD || MI->getOpcode() ==ARM::VSTMD_UPD) &&
- MI->getOperand(0).getReg() == ARM::SP) {
- const MachineOperand &MO1 = MI->getOperand(2);
- if (ARM_AM::getAM4SubMode(MO1.getImm()) == ARM_AM::db) {
- OS << '\t' << "vpush";
- printPredicateOperand(MI, 3, OS);
- OS << '\t';
- printRegisterList(MI, 5, OS);
- }
+ MI->getOperand(0).getReg() == ARM::SP &&
+ ARM_AM::getAM4SubMode(MI->getOperand(2).getImm()) == ARM_AM::db) {
+ OS << '\t' << "vpush";
+ printPredicateOperand(MI, 3, OS);
+ OS << '\t';
+ printRegisterList(MI, 5, OS);
} else
// A8.6.354 VPOP
if ((MI->getOpcode() == ARM::VLDMS_UPD || MI->getOpcode() ==ARM::VLDMD_UPD) &&
- MI->getOperand(0).getReg() == ARM::SP) {
- const MachineOperand &MO1 = MI->getOperand(2);
- if (ARM_AM::getAM4SubMode(MO1.getImm()) == ARM_AM::ia) {
- OS << '\t' << "vpop";
- printPredicateOperand(MI, 3, OS);
- OS << '\t';
- printRegisterList(MI, 5, OS);
- }
+ MI->getOperand(0).getReg() == ARM::SP &&
+ ARM_AM::getAM4SubMode(MI->getOperand(2).getImm()) == ARM_AM::ia) {
+ OS << '\t' << "vpop";
+ printPredicateOperand(MI, 3, OS);
+ OS << '\t';
+ printRegisterList(MI, 5, OS);
} else
printInstruction(MI, OS);
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