[llvm-commits] [llvm] r114021 - in /llvm/trunk: lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp test/MC/Disassembler/neon-tests.txt

[Jim Grosbach]

Author: grosbach
Date: Wed Sep 15 16:04:54 2010
New Revision: 114021

URL: http://llvm.org/viewvc/llvm-project?rev=114021&view=rev
Log:
Teach the MC disassembler to handle vmov.f32 and vmov.f64 immediate to register
moves. Previously, the immediate was printed as the encoded integer value,
which is incorrect.

Modified:
    llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
    llvm/trunk/test/MC/Disassembler/neon-tests.txt

Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp?rev=114021&r1=114020&r2=114021&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp Wed Sep 15 16:04:54 2010
@@ -1573,8 +1573,7 @@
 }
 
 // A7.5.1
-#if 0
-static uint64_t VFPExpandImm(unsigned char byte, unsigned N) {
+static APInt VFPExpandImm(unsigned char byte, unsigned N) {
   assert(N == 32 || N == 64);
 
   uint64_t Result;
@@ -1593,9 +1592,8 @@
     else
       Result |= 0x1L << 62;
   }
-  return Result;
+  return APInt(N, Result);
 }
-#endif
 
 // VFP Unary Format Instructions:
 //
@@ -1972,10 +1970,11 @@
   // Extract/decode the f64/f32 immediate.
   if (OpIdx < NumOps && OpInfo[OpIdx].RegClass < 0
         && !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef()) {
-    // The asm syntax specifies the before-expanded <imm>.
-    // Not VFPExpandImm(slice(insn,19,16) << 4 | slice(insn, 3, 0),
-    //                  Opcode == ARM::FCONSTD ? 64 : 32)
-    MI.addOperand(MCOperand::CreateImm(slice(insn,19,16)<<4 | slice(insn,3,0)));
+    // The asm syntax specifies the floating point value, not the 8-bit literal.
+    APInt immRaw = VFPExpandImm(slice(insn,19,16) << 4 | slice(insn, 3, 0),
+                             Opcode == ARM::FCONSTD ? 64 : 32);
+    MI.addOperand(MCOperand::CreateFPImm(APFloat(immRaw, true)));
+
     ++OpIdx;
   }
 

Modified: llvm/trunk/test/MC/Disassembler/neon-tests.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/neon-tests.txt?rev=114021&r1=114020&r2=114021&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/neon-tests.txt (original)
+++ llvm/trunk/test/MC/Disassembler/neon-tests.txt Wed Sep 15 16:04:54 2010
@@ -51,3 +51,5 @@
 # CHECK:	vtbx.8	d18, {d4, d5, d6}, d7
 0x47 0x2a 0xf4 0xf3
 
+# CHECK: vmov.f32 s0, #5.000000e-01
+0x00 0x0a 0xb6 0xee