[llvm-commits] [llvm] r113980 - in /llvm/trunk: lib/Target/ARM/ARMBaseInstrInfo.cpp test/CodeGen/ARM/arm-and-tst-peephole.ll

[Gabor Greif]

Author: ggreif
Date: Wed Sep 15 11:53:07 2010
New Revision: 113980

URL: http://llvm.org/viewvc/llvm-project?rev=113980&view=rev
Log:
the darwin9-powerpc buildbot keeps consistently crashing,
backing out following to get it back to green,
so I can investigate in peace:

svn merge -c -113840  llvm/test/CodeGen/ARM/arm-and-tst-peephole.ll
svn merge -c -113876 -c -113839 llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp

Modified:
    llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
    llvm/trunk/test/CodeGen/ARM/arm-and-tst-peephole.ll

Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=113980&r1=113979&r2=113980&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Wed Sep 15 11:53:07 2010
@@ -1352,20 +1352,6 @@
     SrcReg = MI->getOperand(0).getReg();
     CmpValue = MI->getOperand(1).getImm();
     return true;
-  case ARM::TSTri: {
-      if (&*MI->getParent()->begin() == MI)
-        return false;
-      const MachineInstr *AND = llvm::prior(MI);
-      if (AND->getOpcode() != ARM::ANDri)
-        return false;
-      if (MI->getOperand(0).getReg() == AND->getOperand(1).getReg() &&
-          MI->getOperand(1).getImm() == AND->getOperand(2).getImm()) {
-        SrcReg = AND->getOperand(0).getReg();
-        CmpValue = 0;
-        return true;
-      }
-    }
-    break;
   }
 
   return false;
@@ -1415,8 +1401,6 @@
   switch (MI->getOpcode()) {
   default: break;
   case ARM::ADDri:
-  case ARM::ANDri:
-  case ARM::t2ANDri:
   case ARM::SUBri:
   case ARM::t2ADDri:
   case ARM::t2SUBri:

Modified: llvm/trunk/test/CodeGen/ARM/arm-and-tst-peephole.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/arm-and-tst-peephole.ll?rev=113980&r1=113979&r2=113980&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/arm-and-tst-peephole.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/arm-and-tst-peephole.ll Wed Sep 15 11:53:07 2010
@@ -17,7 +17,8 @@
   %tmp2 = load i8** %scevgep5
   %0 = ptrtoint i8* %tmp2 to i32
 
-; CHECK:      ands r12, r12, #3
+; CHECK:      and lr, r12, #3
+; CHECK-NEXT: tst r12, #3
 ; CHECK-NEXT: beq LBB0_4
 
 ; T2:      movs r5, #3