[llvm-commits] [llvm] r113875 - /llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp

[Jakob Stoklund Olesen]

On Sep 14, 2010, at 3:20 PM, Jim Grosbach wrote:

> Author: grosbach
> Date: Tue Sep 14 17:20:33 2010
> New Revision: 113875
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=113875&view=rev
> Log:
> The register specified for a dregpair is the corresponding Q register, so to
> get the pair, we need to look up the sub-regs based on the qreg. Create a
> lookup function since we don't have access to TargetRegisterInfo here to
> be able to use getSubReg(ARM::dsub_[01]).

> +// Get the constituent sub-regs for a dregpair from a Q register.
> +static std::pair<unsigned, unsigned> GetDRegPair(unsigned QReg) {
> +  switch (QReg) {
> +  case ARM::Q0:  return std::pair<unsigned, unsigned>(ARM::D0,  ARM::D1);
> +  case ARM::Q1:  return std::pair<unsigned, unsigned>(ARM::D2,  ARM::D3);
> +  case ARM::Q2:  return std::pair<unsigned, unsigned>(ARM::D4,  ARM::D5);
> +  case ARM::Q3:  return std::pair<unsigned, unsigned>(ARM::D6,  ARM::D7);
> +  case ARM::Q4:  return std::pair<unsigned, unsigned>(ARM::D8,  ARM::D9);
> +  case ARM::Q5:  return std::pair<unsigned, unsigned>(ARM::D10, ARM::D11);
> +  case ARM::Q6:  return std::pair<unsigned, unsigned>(ARM::D12, ARM::D13);
> +  case ARM::Q7:  return std::pair<unsigned, unsigned>(ARM::D14, ARM::D15);
> +  case ARM::Q8:  return std::pair<unsigned, unsigned>(ARM::D16, ARM::D17);
> +  case ARM::Q9:  return std::pair<unsigned, unsigned>(ARM::D18, ARM::D19);
> +  case ARM::Q10: return std::pair<unsigned, unsigned>(ARM::D20, ARM::D21);
> +  case ARM::Q11: return std::pair<unsigned, unsigned>(ARM::D22, ARM::D23);
> +  case ARM::Q12: return std::pair<unsigned, unsigned>(ARM::D24, ARM::D25);
> +  case ARM::Q13: return std::pair<unsigned, unsigned>(ARM::D26, ARM::D27);
> +  case ARM::Q14: return std::pair<unsigned, unsigned>(ARM::D28, ARM::D29);
> +  case ARM::Q15: return std::pair<unsigned, unsigned>(ARM::D30, ARM::D31);

I am not really sure if I want to encourage this or not, but the registers are in fact sorted numerically, so you can go:

unsigned DReg = ARM::D0 + 2*(QReg - ARM::Q0)

This requires at least 'assert(Q0+15 == Q15)'

Either way is gross.