[llvm-commits] [llvm] r113670 - in /llvm/trunk: include/llvm/Target/TargetInstrInfo.h lib/CodeGen/PeepholeOptimizer.cpp lib/Target/ARM/ARMBaseInstrInfo.cpp lib/Target/ARM/ARMBaseInstrInfo.h

[Gabor Greif]

On Sep 12, 2:22 am, Bill Wendling <wendl... at apple.com> wrote:
> On Sep 11, 2010, at 12:49 AM, Gabor Greif wrote:
>
>
>
> > Bill,
>
> > you might be interested in my dabbling attempts
> > withhttp://llvm.org/bugs/show_bug.cgi?id=8125
> > The x86 peephole already manages to eliminate
> > the test after the 'and', It would be interesting
> > to see whether ARM does too.
> > Btw., my commit is not really restricted to 'and',
> > any operation that sets the zero flag will do.
>
> > A.t.m. (before your changes) I got:
> > LBB0_1:                                 @ %tailrecurse
> >                                        @ =>This Inner Loop Header:
> > Depth=1
> >        ldr     lr, [r2, #-4]
> >        and     r4, lr, #3
> >        tst     lr, #3
> >        beq     LBB0_4
>
> I saw your patch go through. As with your other code, I don't understand it fully. :) It's certainly an interesting optimization. But I think that we would still need the peephole optimizer for ARM (and PPC?). X86's instructions either always set the EFLAGS register or not. A lot of ARM instructions may set CSPR, but they don't have to. And it appears that that decision needs to wait until after instruction selection...
>

The transformation intends to implement this:

%a = and %something, i32 3  ; a 2-bit mask
switch %a [
case0 ->
case1 ->
case2 ->
case3 ->
]

to

%a = and %something, i32 3  ; a 2-bit mask
%iszero = cmpi %a, i32 0
br %iszero case0 rest

rest:
switch %a [
case1 ->
case2 ->
case3 ->
]

Basically separating out the zero leg from the switch to a place where
the peephole optimizer is more likely to find it. The ARM patch is an
experiment to teach the ARM-peephole optimizer to take advantage of
the hint that the zero-leg is hoisted out. This does not work yet
because of a (suspected by me) bug, where the ARM::ANDri instruction
seems to be dead. It definitely should not be dead. I am investigating
the issue. But I would welcome help why that ANDri is appearing
dead :-)

Cheers,

   Gabor


> -bw
>
> _______________________________________________
> llvm-commits mailing list
> llvm-comm... at cs.uiuc.eduhttp://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits