[llvm-commits] [llvm] r113456 - /llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp

[Bob Wilson]

Author: bwilson
Date: Wed Sep  8 19:38:32 2010
New Revision: 113456

URL: http://llvm.org/viewvc/llvm-project?rev=113456&view=rev
Log:
For double-spaced VLD3/VLD4 instructions, copy the explicit super-register use
operand from the pseudo instruction to the new instruction as an implicit use.
This will preserve any other flags (e.g., kill) on the operand.

Modified:
    llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp?rev=113456&r1=113455&r2=113456&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp Wed Sep  8 19:38:32 2010
@@ -122,13 +122,17 @@
     MIB.addOperand(MI.getOperand(OpIdx++));
 
   MIB = AddDefaultPred(MIB);
-  TransferImpOps(MI, MIB, MIB);
-  // For an instruction writing the odd subregs, add an implicit use of the
-  // super-register because the even subregs were loaded separately.
-  if (RegSpc == EvenDblSpc || RegSpc == OddDblSpc)
-    MIB.addReg(DstReg, RegState::Implicit);
+  // For an instruction writing double-spaced subregs, the pseudo instruction
+  // has an extra operand that is a use of the super-register.  Copy that over
+  // to the new instruction as an implicit operand.
+  if (RegSpc == EvenDblSpc || RegSpc == OddDblSpc) {
+    MachineOperand MO = MI.getOperand(OpIdx);
+    MO.setImplicit(true);
+    MIB.addOperand(MO);
+  }
   // Add an implicit def for the super-register.
   MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
+  TransferImpOps(MI, MIB, MIB);
   MI.eraseFromParent();
 }