[llvm-commits] [llvm] r112664 - in /llvm/trunk: lib/Target/ARM/ARMISelDAGToDAG.cpp lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/ARMInstrThumb2.td test/CodeGen/ARM/mvncc.ll test/CodeGen/Thumb2/thumb2-mvncc.ll

[Evan Cheng]

On Sep 8, 2010, at 3:20 AM, Bill Wendling wrote:

> On Sep 7, 2010, at 11:02 PM, Evan Cheng wrote:
> 
>> Hi Bill,
>> 
>> Thanks for doing this but I have some questions. 
>> 
>> On Aug 31, 2010, at 3:41 PM, Bill Wendling <isanbard at gmail.com> wrote:
>> 
>>> Author: void
>>> Date: Tue Aug 31 17:41:22 2010
>>> New Revision: 112664
>>> 
>>> URL: http://llvm.org/viewvc/llvm-project?rev=112664&view=rev
>>> Log:
>>> We have a chance for an optimization. Consider this code:
>>> 
>>> int x(int t) {
>>> if (t & 256)
>>>  return -26;
>>> return 0;
>>> }
>>> 
>>> We generate this:
>>> 
>>>   tst.w   r0, #256
>>>   mvn     r0, #25
>>>   it      eq
>>>   moveq   r0, #0
>>> 
>>> while gcc generates this:
>>> 
>>>   ands    r0, r0, #256
>>>   it      ne
>>>   mvnne   r0, #25
>>>   bx      lr
>> 
>> Is it possible to generate the "and" and comparison at isel time and let the peephole pass get rid of the compare later? I'd prefer to avoid having these instructions like ARM::ANDS.
>> 
> It's possible. I preferred the isel time change, because it wasn't a hybrid approach. I will try it out though. :-)

Thanks. IMO, one of the big advantage of the machine instruction peephole pass is it avoid having these instruction variants.

Evan

> 
> -bw
>