[llvm-commits] [llvm] r113009 -	/llvm/trunk/lib/Target/X86/X86InstrSSE.td
    Bruno Cardoso Lopes 
    bruno.cardoso at gmail.com
       
    Fri Sep  3 13:44:26 PDT 2010
    
    
  
Author: bruno
Date: Fri Sep  3 15:44:26 2010
New Revision: 113009
URL: http://llvm.org/viewvc/llvm-project?rev=113009&view=rev
Log:
Reapply last harmless part of r112934, the pattern fragment to match X86Unpcklpd
Modified:
    llvm/trunk/lib/Target/X86/X86InstrSSE.td
Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=113009&r1=113008&r2=113009&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Fri Sep  3 15:44:26 2010
@@ -5819,6 +5819,13 @@
 def : Pat<(v2f64 (X86Movlhpd VR128:$src1,
                     (scalar_to_vector (loadf64 addr:$src2)))),
           (MOVHPDrm VR128:$src1, addr:$src2)>;
+// FIXME: Instead of X86Unpcklpd, there should be a X86Movlhpd here, the problem
+// is during lowering, where it's not possible to recognize the load fold cause
+// it has two uses through a bitcast. One use disappears at isel time and the
+// fold opportunity reappears.
+def : Pat<(v2f64 (X86Unpcklpd VR128:$src1,
+                    (scalar_to_vector (loadf64 addr:$src2)))),
+          (MOVHPDrm VR128:$src1, addr:$src2)>;
 
 // Shuffle with MOVSS
 def : Pat<(v4f32 (X86Movss VR128:$src1, (scalar_to_vector FR32:$src2))),
    
    
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