[llvm-commits] [llvm] r112752 - /llvm/trunk/lib/Target/ARM/ARMFastISel.cpp

[Eric Christopher]

Author: echristo
Date: Wed Sep  1 17:16:27 2010
New Revision: 112752

URL: http://llvm.org/viewvc/llvm-project?rev=112752&view=rev
Log:
Some basic store support.

Modified:
    llvm/trunk/lib/Target/ARM/ARMFastISel.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=112752&r1=112751&r2=112752&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Wed Sep  1 17:16:27 2010
@@ -106,6 +106,7 @@
   
     // Instruction selection routines.
     virtual bool ARMSelectLoad(const Instruction *I);
+    virtual bool ARMSelectStore(const Instruction *I);
 
     // Utility routines.
   private:
@@ -113,6 +114,7 @@
     bool isLoadTypeLegal(const Type *Ty, EVT &VT);
     bool ARMEmitLoad(EVT VT, unsigned &ResultReg, unsigned Reg, int Offset);
     bool ARMLoadAlloca(const Instruction *I);
+    bool ARMStoreAlloca(const Instruction *I);
     bool ARMComputeRegOffset(const Value *Obj, unsigned &Reg, int &Offset);
     
     bool DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR);
@@ -444,6 +446,43 @@
   return true;
 }
 
+bool ARMFastISel::ARMStoreAlloca(const Instruction *I) {
+  Value *Op1 = I->getOperand(1);
+
+  // Verify it's an alloca.
+  if (const AllocaInst *AI = dyn_cast<AllocaInst>(Op1)) {
+    DenseMap<const AllocaInst*, int>::iterator SI =
+      FuncInfo.StaticAllocaMap.find(AI);
+
+    if (SI != FuncInfo.StaticAllocaMap.end()) {
+      TargetRegisterClass* RC = TLI.getRegClassFor(TLI.getPointerTy());
+      unsigned Reg = getRegForValue(I->getOperand(0));
+      // Make sure we can get this into a register.
+      if (Reg == 0) return false;
+      TII.storeRegToStackSlot(*FuncInfo.MBB, *FuncInfo.InsertPt,
+                              Reg, true /*isKill*/, SI->second, RC,
+                              TM.getRegisterInfo());
+      return true;
+    }
+  }
+  return false;
+}
+
+bool ARMFastISel::ARMSelectStore(const Instruction *I) {
+  // If we're an alloca we know we have a frame index and can emit the store
+  // quickly.
+  if (ARMStoreAlloca(I))
+    return true;
+    
+  // Yay type legalization
+  EVT VT;
+  if (!isLoadTypeLegal(I->getType(), VT))
+    return false;
+    
+  return false;
+  
+}
+
 bool ARMFastISel::ARMSelectLoad(const Instruction *I) {
   // If we're an alloca we know we have a frame index and can emit the load
   // directly in short order.
@@ -496,6 +535,8 @@
   switch (I->getOpcode()) {
     case Instruction::Load:
       return ARMSelectLoad(I);
+    case Instruction::Store:
+      return ARMSelectStore(I);
     default: break;
   }
   return false;