[llvm-commits] [llvm] r112128 - in /llvm/trunk/lib/Target/X86: X86InstrInfo.h X86MCCodeEmitter.cpp

[Bruno Cardoso Lopes]

Forgot to mention, patch by Dimitry Andric!

On Wed, Aug 25, 2010 at 6:02 PM, Bruno Cardoso Lopes
<bruno.cardoso at gmail.com> wrote:
> Author: bruno
> Date: Wed Aug 25 20:02:53 2010
> New Revision: 112128
>
> URL: http://llvm.org/viewvc/llvm-project?rev=112128&view=rev
> Log:
> Fix PR7748 without using microsoft extensions
>
> Modified:
>    llvm/trunk/lib/Target/X86/X86InstrInfo.h
>    llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp
>
> Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.h?rev=112128&r1=112127&r2=112128&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86InstrInfo.h (original)
> +++ llvm/trunk/lib/Target/X86/X86InstrInfo.h Wed Aug 25 20:02:53 2010
> @@ -445,27 +445,27 @@
>
>     //===------------------------------------------------------------------===//
>     // VEX - The opcode prefix used by AVX instructions
> -    VEX         = 1ULL << 32,
> +    VEX         = 1U << 0,
>
>     // VEX_W - Has a opcode specific functionality, but is used in the same
>     // way as REX_W is for regular SSE instructions.
> -    VEX_W       = 1ULL << 33,
> +    VEX_W       = 1U << 1,
>
>     // VEX_4V - Used to specify an additional AVX/SSE register. Several 2
>     // address instructions in SSE are represented as 3 address ones in AVX
>     // and the additional register is encoded in VEX_VVVV prefix.
> -    VEX_4V      = 1ULL << 34,
> +    VEX_4V      = 1U << 2,
>
>     // VEX_I8IMM - Specifies that the last register used in a AVX instruction,
>     // must be encoded in the i8 immediate field. This usually happens in
>     // instructions with 4 operands.
> -    VEX_I8IMM   = 1ULL << 35,
> +    VEX_I8IMM   = 1U << 3,
>
>     // VEX_L - Stands for a bit in the VEX opcode prefix meaning the current
>     // instruction uses 256-bit wide registers. This is usually auto detected if
>     // a VR256 register is used, but some AVX instructions also have this field
>     // marked when using a f256 memory references.
> -    VEX_L       = 1ULL << 36
> +    VEX_L       = 1U << 4
>   };
>
>   // getBaseOpcodeFor - This function returns the "base" X86 opcode for the
> @@ -533,7 +533,7 @@
>     case X86II::MRMDestMem:
>       return 0;
>     case X86II::MRMSrcMem: {
> -      bool HasVEX_4V = TSFlags & X86II::VEX_4V;
> +      bool HasVEX_4V = (TSFlags >> 32) & X86II::VEX_4V;
>       unsigned FirstMemOp = 1;
>       if (HasVEX_4V)
>         ++FirstMemOp;// Skip the register source (which is encoded in VEX_VVVV).
>
> Modified: llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp?rev=112128&r1=112127&r2=112128&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp Wed Aug 25 20:02:53 2010
> @@ -365,7 +365,7 @@
>                                            const TargetInstrDesc &Desc,
>                                            raw_ostream &OS) const {
>   bool HasVEX_4V = false;
> -  if (TSFlags & X86II::VEX_4V)
> +  if ((TSFlags >> 32) & X86II::VEX_4V)
>     HasVEX_4V = true;
>
>   // VEX_R: opcode externsion equivalent to REX.R in
> @@ -429,10 +429,10 @@
>   if (TSFlags & X86II::OpSize)
>     VEX_PP = 0x01;
>
> -  if (TSFlags & X86II::VEX_W)
> +  if ((TSFlags >> 32) & X86II::VEX_W)
>     VEX_W = 1;
>
> -  if (TSFlags & X86II::VEX_L)
> +  if ((TSFlags >> 32) & X86II::VEX_L)
>     VEX_L = 1;
>
>   switch (TSFlags & X86II::Op0Mask) {
> @@ -501,7 +501,7 @@
>
>     // If the last register should be encoded in the immediate field
>     // do not use any bit from VEX prefix to this register, ignore it
> -    if (TSFlags & X86II::VEX_I8IMM)
> +    if ((TSFlags >> 32) & X86II::VEX_I8IMM)
>       NumOps--;
>
>     for (; CurOp != NumOps; ++CurOp) {
> @@ -801,9 +801,9 @@
>   // It uses the VEX.VVVV field?
>   bool HasVEX_4V = false;
>
> -  if (TSFlags & X86II::VEX)
> +  if ((TSFlags >> 32) & X86II::VEX)
>     HasVEXPrefix = true;
> -  if (TSFlags & X86II::VEX_4V)
> +  if ((TSFlags >> 32) & X86II::VEX_4V)
>     HasVEX_4V = true;
>
>   // Determine where the memory operand starts, if present.
> @@ -955,7 +955,7 @@
>   if (CurOp != NumOps) {
>     // The last source register of a 4 operand instruction in AVX is encoded
>     // in bits[7:4] of a immediate byte, and bits[3:0] are ignored.
> -    if (TSFlags & X86II::VEX_I8IMM) {
> +    if ((TSFlags >> 32) & X86II::VEX_I8IMM) {
>       const MCOperand &MO = MI.getOperand(CurOp++);
>       bool IsExtReg =
>         X86InstrInfo::isX86_64ExtendedReg(MO.getReg());
>
>
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-- 
Bruno Cardoso Lopes
http://www.brunocardoso.cc