[llvm-commits] [llvm] r111883 - /llvm/trunk/lib/Target/ARM/ARMFastISel.cpp

[Jim Grosbach]

On Aug 23, 2010, at 5:50 PM, Eric Christopher wrote:

> Author: echristo
> Date: Mon Aug 23 19:50:47 2010
> New Revision: 111883
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=111883&view=rev
> Log:
> Add register class hack that needs to go away, but makes it more obvious
> that it needs to go away.  Use loadRegFromStackSlot where possible.
> 
> Also, remember to update the value map.
> 
> Modified:
>    llvm/trunk/lib/Target/ARM/ARMFastISel.cpp
> 
> Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=111883&r1=111882&r2=111883&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Mon Aug 23 19:50:47 2010
> @@ -58,6 +58,9 @@
>   const TargetInstrInfo &TII;
>   const TargetLowering &TLI;
>   const ARMFunctionInfo *AFI;
> +  
> +  // FIXME: Remove this and replace it with queries.
> +  const TargetRegisterClass *FixedRC;
> 
>   public:
>     explicit ARMFastISel(FunctionLoweringInfo &funcInfo) 
> @@ -67,6 +70,7 @@
>       TLI(*TM.getTargetLowering()) {
>       Subtarget = &TM.getSubtarget<ARMSubtarget>();
>       AFI = funcInfo.MF->getInfo<ARMFunctionInfo>();
> +      FixedRC = ARM::GPRRegisterClass;
>     }
> 
>     // Code from FastISel.cpp.
> @@ -109,6 +113,7 @@
> 
>     // Utility routines.
>   private:
> +    bool ARMLoadAlloca(const Instruction *I);
>     bool ARMComputeRegOffset(const Value *Obj, unsigned &Reg, int &Offset);
> 
>     bool DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR);
> @@ -340,22 +345,14 @@
>     //errs() << "Failing Opcode is: " << *Op1 << "\n";
>     break;
>     case Instruction::Alloca: {
> -      // Do static allocas.
> -      const AllocaInst *A = cast<AllocaInst>(Obj);
> -      DenseMap<const AllocaInst*, int>::iterator SI =
> -        FuncInfo.StaticAllocaMap.find(A);
> -      if (SI != FuncInfo.StaticAllocaMap.end())
> -        Offset =
> -          TM.getRegisterInfo()->getFrameIndexReference(*FuncInfo.MF,
> -                                                       SI->second, Reg);
> -      else
> -        return false;
> -      return true;
> +      assert(false && "Alloca should have been handled earlier!");
> +      return false;
>     }
>   }
> 
>   if (const GlobalValue *GV = dyn_cast<GlobalValue>(Obj)) {
>     //errs() << "Failing GV is: " << GV << "\n";
> +    (void)GV;
>     return false;
>   }
> 
> @@ -364,12 +361,37 @@
>   return Reg != 0;  
> }
> 
> +bool ARMFastISel::ARMLoadAlloca(const Instruction *I) {
> +  Value *Op0 = I->getOperand(0);
> +
> +  // Verify it's an alloca.
> +  const Instruction *Inst = dyn_cast<Instruction>(Op0);
> +  if (!Inst || Inst->getOpcode() != Instruction::Alloca) return false;
> +
> +  const AllocaInst *AI = cast<AllocaInst>(Op0);

You can combine these checks and the following cast to AllocaInst with:

if (const AllocaInst *AI = dyn_cast<AllocaInst>(Op0) {
 ...

> +  DenseMap<const AllocaInst*, int>::iterator SI =
> +    FuncInfo.StaticAllocaMap.find(AI);
> +    
> +  if (SI != FuncInfo.StaticAllocaMap.end()) {
> +    unsigned ResultReg = createResultReg(FixedRC);
> +    TII.loadRegFromStackSlot(*FuncInfo.MBB, *FuncInfo.InsertPt,
> +                              ResultReg, SI->second, FixedRC,
> +                              TM.getRegisterInfo());
> +    UpdateValueMap(I, ResultReg);
> +    return true;
> +  }
> +  
> +  return false;
> +}
> +
> bool ARMFastISel::ARMSelectLoad(const Instruction *I) {
>   // Our register and offset with innocuous defaults.
>   unsigned Reg = 0;
>   int Offset = 0;
> 
>   // TODO: Think about using loadRegFromStackSlot() here when we can.
> +  if (ARMLoadAlloca(I))
> +    return true;
> 
>   // See if we can handle this as Reg + Offset
>   if (!ARMComputeRegOffset(I->getOperand(0), Reg, Offset))
> @@ -393,10 +415,11 @@
>   } 
> 
>   // FIXME: There is more than one register class in the world...
> -  unsigned ResultReg = createResultReg(ARM::GPRRegisterClass);
> +  unsigned ResultReg = createResultReg(FixedRC);
>   AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
>                           TII.get(ARM::LDR), ResultReg)
>                   .addImm(0).addReg(Reg).addImm(Offset));
> +  UpdateValueMap(I, ResultReg);
> 
>   return true;
> }
> 
> 
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