[llvm-commits] [llvm] r111885 - /llvm/trunk/lib/Target/ARM/ARMFastISel.cpp

[Jim Grosbach]

On Aug 23, 2010, at 6:10 PM, Eric Christopher wrote:

> Author: echristo
> Date: Mon Aug 23 20:10:04 2010
> New Revision: 111885
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=111885&view=rev
> Log:
> Fix the opcode and the operands for the load instruction.
> 
> Modified:
>    llvm/trunk/lib/Target/ARM/ARMFastISel.cpp
> 
> Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=111885&r1=111884&r2=111885&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Mon Aug 23 20:10:04 2010
> @@ -415,10 +415,13 @@
>   } 
> 
>   // FIXME: There is more than one register class in the world...
> +  // TODO: Verify the additions above work, otherwise we'll need to add the
> +  // offset instead of 0 and do all sorts of operand munging.
>   unsigned ResultReg = createResultReg(FixedRC);
> +  unsigned Opc = AFI->isThumb2Function() ? ARM::tLDR : ARM::LDR;

You probably want ARM::t2LDR for the Thumb2 side. tLDR will work, but is the Thumb1 (16-bit wide) encoding and has more restrictive encodings.


>   AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
> -                          TII.get(ARM::LDR), ResultReg)
> -                  .addImm(0).addReg(Reg).addImm(Offset));
> +                          TII.get(Opc), ResultReg)
> +                  .addReg(Reg).addReg(0).addImm(0));
>   UpdateValueMap(I, ResultReg);
> 
>   return true;
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits