[llvm-commits] [llvm] r111837 - /llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

[Chris Lattner]

On Aug 23, 2010, at 1:41 PM, Bruno Cardoso Lopes wrote:
> URL: http://llvm.org/viewvc/llvm-project?rev=111837&view=rev
> Log:
> Start using target speficic nodes for shuffles: pshufhw and pshuflw

Cool!

> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Mon Aug 23 15:41:02 2010
> @@ -2558,6 +2558,18 @@
> //                           Other Lowering Hooks
> //===----------------------------------------------------------------------===//
> 
> +static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
> +              SDValue V1, SDValue V2, unsigned TargetMask, SelectionDAG &DAG) {

Should this be named something like "getPSHUF" or do you plan to expand this to other shuffle nodes that take an i8 immediate?  getTargetShuffleNode seems like an overly generic name.

-Chris

> +
> +  switch(Opc) {
> +  default: llvm_unreachable("Unknown x86 shuffle node");
> +  case X86ISD::PSHUFHW:
> +  case X86ISD::PSHUFLW:
> +    return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
> +  }
> +
> +  return SDValue();
> +}
> 
> SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
>   MachineFunction &MF = DAG.getMachineFunction();
> @@ -4266,8 +4278,14 @@
>     // If we've eliminated the use of V2, and the new mask is a pshuflw or
>     // pshufhw, that's as cheap as it gets.  Return the new shuffle.
>     if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
> -      return DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
> +      unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
> +      unsigned TargetMask = 0;
> +      NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
>                                   DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
> +      TargetMask = pshufhw ? X86::getShufflePSHUFHWImmediate(NewV.getNode()):
> +                             X86::getShufflePSHUFLWImmediate(NewV.getNode());
> +      V1 = NewV.getOperand(0);
> +      return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, V1, TargetMask, DAG);
>     }
>   }
> 
> 
> 
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