[llvm-commits] PATCH: implement vector zext when vector types are legal (neon)

[Bob Wilson]

On Aug 18, 2010, at 8:48 AM, Bob Wilson wrote:
> 
> I'm looking now at all the NEON intrinsics for basic operations that extend one or both operands, and I can't figure out why they were ever needed.  I'm starting to think that I just totally screwed that up.  We should be able to avoid the intrinsics and represent those operations with zero_extend and sign_extend patterns.  That would also avoid the need for the DAG combine pattern for vmlal.
> 
> I'll give that a try.  We'll either end up with a better solution or I'll remember why I did it that way in the first place.

I remembered.

At the time I added the NEON port, zero_extend and sign_extend did not work with vector types, so we decided to just go with intrinsics.  The situation may have improved since then, but there are still issues.  The DAG combiner really wants to form extending loads, whether the target says they are legal for vectors or not, and then legalization fails to correctly handle the expansion of the extending loads.  There may be others.

It would be nice to avoid using intrinsics for these things, so I'll see if I can work through the issues without spending too much time on it.