[llvm-commits] [llvm] r111057 - in /llvm/trunk: lib/Target/ARM/ARMInstrThumb2.td test/MC/Disassembler/thumb-tests.txt

[Bob Wilson]

Author: bwilson
Date: Fri Aug 13 18:24:25 2010
New Revision: 111057

URL: http://llvm.org/viewvc/llvm-project?rev=111057&view=rev
Log:
Add a Thumb2 t2RSBrr instruction for disassembly only.
This fixes another part of PR7792.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
    llvm/trunk/test/MC/Disassembler/thumb-tests.txt

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=111057&r1=111056&r2=111057&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Fri Aug 13 18:24:25 2010
@@ -259,9 +259,9 @@
     T2I_bin_irs<opcod, opc, opnode, Commutable, ".w">;
 
 /// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are
-/// reversed. It doesn't define the 'rr' form since it's handled by its
-/// T2I_bin_irs counterpart.
-multiclass T2I_rbin_is<bits<4> opcod, string opc, PatFrag opnode> {
+/// reversed.  The 'rr' form is only defined for the disassembler; for codegen
+/// it is equivalent to the T2I_bin_irs counterpart.
+multiclass T2I_rbin_irs<bits<4> opcod, string opc, PatFrag opnode> {
    // shifted imm
    def ri : T2sI<(outs rGPR:$dst), (ins rGPR:$rhs, t2_so_imm:$lhs), IIC_iALUi,
                  opc, ".w\t$dst, $rhs, $lhs",
@@ -272,6 +272,18 @@
      let Inst{20} = ?; // The S bit.
      let Inst{15} = 0;
    }
+   // register
+   def rr : T2sI<(outs rGPR:$dst), (ins rGPR:$rhs, rGPR:$lhs), IIC_iALUr,
+                 opc, "\t$dst, $rhs, $lhs",
+                 [(set rGPR:$dst, (opnode rGPR:$lhs, rGPR:$rhs))]> {
+     let Inst{31-27} = 0b11101;
+     let Inst{26-25} = 0b01;
+     let Inst{24-21} = opcod;
+     let Inst{20} = ?; // The S bit.
+     let Inst{14-12} = 0b000; // imm3
+     let Inst{7-6} = 0b00; // imm2
+     let Inst{5-4} = 0b00; // type
+   }
    // shifted register
    def rs : T2sI<(outs rGPR:$dst), (ins rGPR:$rhs, t2_so_reg:$lhs), IIC_iALUsi,
                  opc, "\t$dst, $rhs, $lhs",
@@ -461,7 +473,8 @@
 }
 }
 
-/// T2I_rbin_s_is - Same as T2I_rbin_is except sets 's' bit.
+/// T2I_rbin_s_is - Same as T2I_rbin_irs except sets 's' bit and the register
+/// version is not needed since this is only for codegen.
 let Defs = [CPSR] in {
 multiclass T2I_rbin_s_is<bits<4> opcod, string opc, PatFrag opnode> {
    // shifted imm
@@ -1387,7 +1400,7 @@
                           BinOpFrag<(sube_live_carry node:$LHS, node:$RHS)>>;
 
 // RSB
-defm t2RSB  : T2I_rbin_is   <0b1110, "rsb",
+defm t2RSB  : T2I_rbin_irs  <0b1110, "rsb",
                              BinOpFrag<(sub  node:$LHS, node:$RHS)>>;
 defm t2RSBS : T2I_rbin_s_is <0b1110, "rsb",
                              BinOpFrag<(subc node:$LHS, node:$RHS)>>;

Modified: llvm/trunk/test/MC/Disassembler/thumb-tests.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/thumb-tests.txt?rev=111057&r1=111056&r2=111057&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/thumb-tests.txt (original)
+++ llvm/trunk/test/MC/Disassembler/thumb-tests.txt Fri Aug 13 18:24:25 2010
@@ -51,6 +51,10 @@
 # CHECK:	rsbs	r0, r0, #0
 0x40 0x42
 
+# CHECK-NOT:	rsb	r0, r2, r0, lsl #0
+# CHECK:	rsb	r0, r2, r0
+0xc2 0xeb 0x00 0x00
+
 # CHECK-NOT:	ssat	r0, #17, r12, lsl #0
 # CHECK:	ssat	r0, #17, r12
 0x0c 0xf3 0x10 0x00