[llvm-commits] [llvm] r110880 - in /llvm/trunk: lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h test/MC/Disassembler/arm-tests.txt

[Johnny Chen]

Author: johnny
Date: Wed Aug 11 18:35:12 2010
New Revision: 110880

URL: http://llvm.org/viewvc/llvm-project?rev=110880&view=rev
Log:
Changed the format of DMBsy, DSBsy, and friends from Pseudo to MiscFrm.
Added two test cases to arm-tests.txt.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
    llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
    llvm/trunk/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h
    llvm/trunk/test/MC/Disassembler/arm-tests.txt

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=110880&r1=110879&r2=110880&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Wed Aug 11 18:35:12 2010
@@ -2356,7 +2356,7 @@
 
 // memory barriers protect the atomic sequences
 let hasSideEffects = 1 in {
-def DMBsy : AInoP<(outs), (ins), Pseudo, NoItinerary, "dmb", "",
+def DMBsy : AInoP<(outs), (ins), MiscFrm, NoItinerary, "dmb", "",
                   [(ARMMemBarrier)]>, Requires<[IsARM, HasDB]> {
   let Inst{31-4} = 0xf57ff05;
   // FIXME: add support for options other than a full system DMB
@@ -2364,7 +2364,7 @@
   let Inst{3-0} = 0b1111;
 }
 
-def DSBsy : AInoP<(outs), (ins), Pseudo, NoItinerary, "dsb", "",
+def DSBsy : AInoP<(outs), (ins), MiscFrm, NoItinerary, "dsb", "",
                   [(ARMSyncBarrier)]>, Requires<[IsARM, HasDB]> {
   let Inst{31-4} = 0xf57ff04;
   // FIXME: add support for options other than a full system DSB
@@ -2372,7 +2372,7 @@
   let Inst{3-0} = 0b1111;
 }
 
-def DMB_MCR : AInoP<(outs), (ins GPR:$zero), Pseudo, NoItinerary,
+def DMB_MCR : AInoP<(outs), (ins GPR:$zero), MiscFrm, NoItinerary,
                        "mcr", "\tp15, 0, $zero, c7, c10, 5",
                        [(ARMMemBarrierMCR GPR:$zero)]>,
                        Requires<[IsARM, HasV6]> {
@@ -2380,7 +2380,7 @@
   // FIXME: add encoding
 }
 
-def DSB_MCR : AInoP<(outs), (ins GPR:$zero), Pseudo, NoItinerary,
+def DSB_MCR : AInoP<(outs), (ins GPR:$zero), MiscFrm, NoItinerary,
                         "mcr", "\tp15, 0, $zero, c7, c10, 4",
                         [(ARMSyncBarrierMCR GPR:$zero)]>,
                         Requires<[IsARM, HasV6]> {

Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp?rev=110880&r1=110879&r2=110880&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp Wed Aug 11 18:35:12 2010
@@ -493,9 +493,6 @@
 static bool DisassemblePseudo(MCInst &MI, unsigned Opcode, uint32_t insn,
     unsigned short NumOps, unsigned &NumOpsAdded, BO) {
 
-  if (Opcode == ARM::DMBsy || Opcode == ARM::DSBsy)
-    return true;
-
   assert(0 && "Unexpected pseudo instruction!");
   return false;
 }

Modified: llvm/trunk/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h?rev=110880&r1=110879&r2=110880&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h Wed Aug 11 18:35:12 2010
@@ -1629,8 +1629,8 @@
 // A8.6.26
 // t2BXJ -> Rn
 //
-// Miscellaneous control: t2Int_MemBarrierV7 (and its t2DMB variants),
-// t2Int_SyncBarrierV7 (and its t2DSB varianst), t2ISBsy, t2CLREX
+// Miscellaneous control: t2DMBsy (and its t2DMB variants),
+// t2DSBsy (and its t2DSB varianst), t2ISBsy, t2CLREX
 //   -> no operand (except pred-imm pred-ccr for CLREX, memory barrier variants)
 //
 // Hint: t2NOP, t2YIELD, t2WFE, t2WFI, t2SEV

Modified: llvm/trunk/test/MC/Disassembler/arm-tests.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/arm-tests.txt?rev=110880&r1=110879&r2=110880&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/arm-tests.txt (original)
+++ llvm/trunk/test/MC/Disassembler/arm-tests.txt Wed Aug 11 18:35:12 2010
@@ -12,9 +12,15 @@
 # CHECK:	cmn	r0, #1
 0x01 0x00 0x70 0xe3
 
+# CHECK:	dmb
+0x5f 0xf0 0x7f 0xf5
+
 # CHECK:	dmb	nshst
 0x56 0xf0 0x7f 0xf5
 
+# CHECK:	dsb
+0x4f 0xf0 0x7f 0xf5
+
 # CHECK:	ldclvc	p5, cr15, [r8], #-0
 0x00 0xf5 0x78 0x7c