[llvm-commits] [llvm] r110786 - in /llvm/trunk: lib/Target/ARM/ARM.td test/CodeGen/Thumb/barrier.ll

[Evan Cheng]

Author: evancheng
Date: Wed Aug 11 01:30:38 2010
New Revision: 110786

URL: http://llvm.org/viewvc/llvm-project?rev=110786&view=rev
Log:
Add Cortex-M0 support. It's a ARMv6m device (no ARM mode) with some 32-bit
instructions: dmb, dsb, isb, msr, and mrs.

Modified:
    llvm/trunk/lib/Target/ARM/ARM.td
    llvm/trunk/test/CodeGen/Thumb/barrier.ll

Modified: llvm/trunk/lib/Target/ARM/ARM.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARM.td?rev=110786&r1=110785&r2=110786&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARM.td (original)
+++ llvm/trunk/lib/Target/ARM/ARM.td Wed Aug 11 01:30:38 2010
@@ -127,6 +127,9 @@
 def : Processor<"mpcorenovfp",      ARMV6Itineraries, [ArchV6]>;
 def : Processor<"mpcore",           ARMV6Itineraries, [ArchV6, FeatureVFP2]>;
 
+// V6M Processors.
+def : Processor<"cortex-m0",        ARMV6Itineraries, [ArchV6, FeatureDB]>;
+
 // V6T2 Processors.
 def : Processor<"arm1156t2-s",     ARMV6Itineraries,
                  [ArchV6T2, FeatureThumb2]>;
@@ -141,6 +144,8 @@
 def : Processor<"cortex-a9",        CortexA9Itineraries,
                 [ArchV7A, FeatureThumb2, FeatureNEON, FeatureT2ExtractPack,
                  FeatureDB]>;
+
+// V7M Processors.
 def : ProcNoItin<"cortex-m3",       [ArchV7M, FeatureThumb2, FeatureHWDiv,
                                      FeatureDB]>;
 def : ProcNoItin<"cortex-m4",       [ArchV7M, FeatureThumb2, FeatureHWDiv,

Modified: llvm/trunk/test/CodeGen/Thumb/barrier.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb/barrier.ll?rev=110786&r1=110785&r2=110786&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb/barrier.ll (original)
+++ llvm/trunk/test/CodeGen/Thumb/barrier.ll Wed Aug 11 01:30:38 2010
@@ -1,17 +1,24 @@
-; RUN: llc < %s -march=thumb -mattr=+v6  | FileCheck %s
+; RUN: llc < %s -march=thumb -mattr=+v6      | FileCheck %s -check-prefix=V6
+; RUN: llc < %s -march=thumb -mcpu=cortex-m0 | FileCheck %s -check-prefix=M0
 
 declare void @llvm.memory.barrier( i1 , i1 , i1 , i1 , i1 )
 
 define void @t1() {
-; CHECK: t1:
-; CHECK: blx {{_*}}sync_synchronize
+; V6: t1:
+; V6: blx {{_*}}sync_synchronize
+
+; M0: t1:
+; M0: dsb
   call void @llvm.memory.barrier( i1 false, i1 false, i1 false, i1 true, i1 true )
   ret void
 }
 
 define void @t2() {
-; CHECK: t2:
-; CHECK: blx {{_*}}sync_synchronize
+; V6: t2:
+; V6: blx {{_*}}sync_synchronize
+
+; M0: t2:
+; M0: dmb
   call void @llvm.memory.barrier( i1 false, i1 false, i1 false, i1 true, i1 false )
   ret void
 }