[llvm-commits] [llvm] r110576 - in /llvm/trunk: lib/Target/CellSPU/SPUISelLowering.cpp lib/Target/CellSPU/SPUISelLowering.h lib/Target/CellSPU/SPUInstrInfo.td lib/Target/CellSPU/SPUNodes.td lib/Target/CellSPU/SPURegisterInfo.cpp test/CodeGen/CellSPU/bigstack.ll test/CodeGen/CellSPU/v2f32.ll
Kalle Raiskila
kalle.raiskila at nokia.com
Mon Aug 9 09:33:01 PDT 2010
Author: kraiskil
Date: Mon Aug 9 11:33:00 2010
New Revision: 110576
URL: http://llvm.org/viewvc/llvm-project?rev=110576&view=rev
Log:
Have SPU handle halfvec stores aligned by 8 bytes.
Modified:
llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp
llvm/trunk/lib/Target/CellSPU/SPUISelLowering.h
llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.td
llvm/trunk/lib/Target/CellSPU/SPUNodes.td
llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp
llvm/trunk/test/CodeGen/CellSPU/bigstack.ll
llvm/trunk/test/CodeGen/CellSPU/v2f32.ll
Modified: llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp?rev=110576&r1=110575&r2=110576&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp Mon Aug 9 11:33:00 2010
@@ -470,6 +470,9 @@
setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
+ setOperationAction(ISD::STORE, MVT::v2i32, Custom);
+ setOperationAction(ISD::STORE, MVT::v2f32, Custom);
+
setShiftAmountType(MVT::i32);
setBooleanContents(ZeroOrNegativeOneBooleanContent);
@@ -518,6 +521,8 @@
node_names[(unsigned) SPUISD::ADD64_MARKER] = "SPUISD::ADD64_MARKER";
node_names[(unsigned) SPUISD::SUB64_MARKER] = "SPUISD::SUB64_MARKER";
node_names[(unsigned) SPUISD::MUL64_MARKER] = "SPUISD::MUL64_MARKER";
+ node_names[(unsigned) SPUISD::HALF2VEC] = "SPUISD::HALF2VEC";
+ node_names[(unsigned) SPUISD::VEC2HALF] = "SPUISD::VEC2HALF";
}
std::map<unsigned, const char *>::iterator i = node_names.find(Opcode);
@@ -738,12 +743,14 @@
EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
DebugLoc dl = Op.getDebugLoc();
unsigned alignment = SN->getAlignment();
+ const bool isVec = VT.isVector();
+ EVT eltTy = isVec ? VT.getVectorElementType(): VT;
switch (SN->getAddressingMode()) {
case ISD::UNINDEXED: {
// The vector type we really want to load from the 16-byte chunk.
EVT vecVT = EVT::getVectorVT(*DAG.getContext(),
- VT, (128 / VT.getSizeInBits()));
+ eltTy, (128 / eltTy.getSizeInBits()));
SDValue alignLoadVec;
SDValue basePtr = SN->getBasePtr();
@@ -752,7 +759,6 @@
if (alignment == 16) {
ConstantSDNode *CN;
-
// Special cases for a known aligned load to simplify the base pointer
// and insertion byte:
if (basePtr.getOpcode() == ISD::ADD
@@ -776,6 +782,9 @@
insertEltOffs = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT,
basePtr,
DAG.getConstant(0, PtrVT));
+ basePtr = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT,
+ basePtr,
+ DAG.getConstant(0, PtrVT));
}
} else {
// Unaligned load: must be more pessimistic about addressing modes:
@@ -812,8 +821,8 @@
DAG.getConstant(0, PtrVT));
}
- // Re-emit as a v16i8 vector load
- alignLoadVec = DAG.getLoad(MVT::v16i8, dl, the_chain, basePtr,
+ // Load the memory to which to store.
+ alignLoadVec = DAG.getLoad(vecVT, dl, the_chain, basePtr,
SN->getSrcValue(), SN->getSrcValueOffset(),
SN->isVolatile(), SN->isNonTemporal(), 16);
@@ -844,11 +853,19 @@
}
#endif
- SDValue insertEltOp =
- DAG.getNode(SPUISD::SHUFFLE_MASK, dl, vecVT, insertEltOffs);
- SDValue vectorizeOp =
- DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, vecVT, theValue);
-
+ SDValue insertEltOp;
+ SDValue vectorizeOp;
+ if (isVec)
+ {
+ // FIXME: this works only if the vector is 64bit!
+ insertEltOp = DAG.getNode(SPUISD::SHUFFLE_MASK, dl, MVT::v2i64, insertEltOffs);
+ vectorizeOp = DAG.getNode(SPUISD::HALF2VEC, dl, vecVT, theValue);
+ }
+ else
+ {
+ insertEltOp = DAG.getNode(SPUISD::SHUFFLE_MASK, dl, vecVT, insertEltOffs);
+ vectorizeOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, vecVT, theValue);
+ }
result = DAG.getNode(SPUISD::SHUFB, dl, vecVT,
vectorizeOp, alignLoadVec,
DAG.getNode(ISD::BIT_CONVERT, dl,
Modified: llvm/trunk/lib/Target/CellSPU/SPUISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelLowering.h?rev=110576&r1=110575&r2=110576&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPUISelLowering.h (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUISelLowering.h Mon Aug 9 11:33:00 2010
@@ -54,6 +54,8 @@
ADD64_MARKER, ///< i64 addition marker
SUB64_MARKER, ///< i64 subtraction marker
MUL64_MARKER, ///< i64 multiply marker
+ HALF2VEC, ///< Promote 64 bit vector to 128 bits
+ VEC2HALF, ///< Extract first 64 bits from 128 bit vector
LAST_SPUISD ///< Last user-defined instruction
};
}
Modified: llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.td?rev=110576&r1=110575&r2=110576&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.td (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.td Mon Aug 9 11:33:00 2010
@@ -1468,6 +1468,9 @@
class ORCvtVecGPRC:
ORCvtForm<(outs GPRC:$rT), (ins VECREG:$rA)>;
+class ORCvtVecVec:
+ ORCvtForm<(outs VECREG:$rT), (ins VECREG:$rA)>;
+
multiclass BitwiseOr
{
def v16i8: ORVecInst<v16i8>;
@@ -1514,6 +1517,13 @@
def f32_v4f32: ORExtractElt<R32FP>;
def f64_v2f64: ORExtractElt<R64FP>;
+ // half <-> full vector mappings
+ def v2i32_v4i32: ORCvtVecVec;
+ def v4i32_v2i32: ORCvtVecVec;
+ def v2f32_v4f32: ORCvtVecVec;
+ def v4f32_v2f32: ORCvtVecVec;
+
+
// Conversion from vector to GPRC
def i128_vec: ORCvtVecGPRC;
@@ -1623,6 +1633,18 @@
def : Pat<(SPUvec2prefslot (v2f64 VECREG:$rA)),
(ORf64_v2f64 VECREG:$rA)>;
+// Conversions between 64 bit and 128 bit vectors.
+
+def : Pat<(v4i32 (SPUhalf2vec (v2i32 VECREG:$rA))),
+ (ORv4i32_v2i32 (v2i32 VECREG:$rA))>;
+def : Pat<(v4f32 (SPUhalf2vec (v2f32 VECREG:$rA))),
+ (ORv4f32_v2f32 (v2f32 VECREG:$rA))>;
+
+def : Pat<(v2i32 (SPUvec2half (v4i32 VECREG:$rA))),
+ (ORv2i32_v4i32 VECREG:$rA)>;
+def : Pat<(v2f32 (SPUvec2half (v4f32 VECREG:$rA))),
+ (ORv2f32_v4f32 VECREG:$rA)>;
+
// Load Register: This is an assembler alias for a bitwise OR of a register
// against itself. It's here because it brings some clarity to assembly
// language output.
Modified: llvm/trunk/lib/Target/CellSPU/SPUNodes.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUNodes.td?rev=110576&r1=110575&r2=110576&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPUNodes.td (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUNodes.td Mon Aug 9 11:33:00 2010
@@ -117,6 +117,12 @@
def SPU_vec_demote : SDTypeProfile<1, 1, []>;
def SPUvec2prefslot: SDNode<"SPUISD::VEC2PREFSLOT", SPU_vec_demote, []>;
+def SPU_half_2_vec : SDTypeProfile<1, 1, []>;
+def SPUhalf2vec: SDNode<"SPUISD::HALF2VEC", SPU_half_2_vec, []>;
+
+def SPU_vec_2_half : SDTypeProfile<1, 1, []>;
+def SPUvec2half: SDNode<"SPUISD::VEC2HALF", SPU_vec_2_half, []>;
+
// Address high and low components, used for [r+r] type addressing
def SPUhi : SDNode<"SPUISD::Hi", SDTIntBinOp, []>;
def SPUlo : SDNode<"SPUISD::Lo", SDTIntBinOp, []>;
Modified: llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp?rev=110576&r1=110575&r2=110576&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp Mon Aug 9 11:33:00 2010
@@ -587,6 +587,7 @@
case SPU::LQDr32: return SPU::LQXr32;
case SPU::LQDr128: return SPU::LQXr128;
case SPU::LQDv16i8: return SPU::LQXv16i8;
+ case SPU::LQDv4i32: return SPU::LQXv4i32;
case SPU::LQDv4f32: return SPU::LQXv4f32;
case SPU::STQDr32: return SPU::STQXr32;
case SPU::STQDr128: return SPU::STQXr128;
Modified: llvm/trunk/test/CodeGen/CellSPU/bigstack.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CellSPU/bigstack.ll?rev=110576&r1=110575&r2=110576&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/CellSPU/bigstack.ll (original)
+++ llvm/trunk/test/CodeGen/CellSPU/bigstack.ll Mon Aug 9 11:33:00 2010
@@ -1,7 +1,7 @@
; RUN: llc < %s -march=cellspu -o %t1.s
-; RUN: grep lqx %t1.s | count 4
-; RUN: grep il %t1.s | grep -v file | count 7
-; RUN: grep stqx %t1.s | count 2
+; RUN: grep lqx %t1.s | count 3
+; RUN: grep il %t1.s | grep -v file | count 5
+; RUN: grep stqx %t1.s | count 1
define i32 @bigstack() nounwind {
entry:
Modified: llvm/trunk/test/CodeGen/CellSPU/v2f32.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CellSPU/v2f32.ll?rev=110576&r1=110575&r2=110576&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/CellSPU/v2f32.ll (original)
+++ llvm/trunk/test/CodeGen/CellSPU/v2f32.ll Mon Aug 9 11:33:00 2010
@@ -61,3 +61,15 @@
ret %vec %rv
}
+define void @test_unaligned_store() {
+;CHECK: cdd $3, 8($3)
+;CHECK: lqd
+;CHECK: shufb
+;CHECK: stqd
+ %data = alloca [4 x float], align 16 ; <[4 x float]*> [#uses=1]
+ %ptr = getelementptr [4 x float]* %data, i32 0, i32 2 ; <float*> [#uses=1]
+ %vptr = bitcast float* %ptr to <2 x float>* ; <[1 x <2 x float>]*> [#uses=1]
+ store <2 x float> undef, <2 x float>* %vptr
+ ret void
+}
+
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