[llvm-commits] [llvm] r109608 - /llvm/trunk/lib/CodeGen/MachineInstr.cpp

[Jim Grosbach]

This is going to be very useful, and not just for those crazy enough to hack on register allocators. ;) Thanks, Jakob.

-Jim

On Jul 28, 2010, at 11:35 AM, Jakob Stoklund Olesen wrote:

> Author: stoklund
> Date: Wed Jul 28 13:35:46 2010
> New Revision: 109608
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=109608&view=rev
> Log:
> Print out the regclass of any virtual registers used by a machine instruction.
> 
> Modified:
>    llvm/trunk/lib/CodeGen/MachineInstr.cpp
> 
> Modified: llvm/trunk/lib/CodeGen/MachineInstr.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineInstr.cpp?rev=109608&r1=109607&r2=109608&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/MachineInstr.cpp (original)
> +++ llvm/trunk/lib/CodeGen/MachineInstr.cpp Wed Jul 28 13:35:46 2010
> @@ -1236,12 +1236,18 @@
> void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM) const {
>   // We can be a bit tidier if we know the TargetMachine and/or MachineFunction.
>   const MachineFunction *MF = 0;
> +  const MachineRegisterInfo *MRI = 0;
>   if (const MachineBasicBlock *MBB = getParent()) {
>     MF = MBB->getParent();
>     if (!TM && MF)
>       TM = &MF->getTarget();
> +    if (MF)
> +      MRI = &MF->getRegInfo();
>   }
> 
> +  // Save a list of virtual registers.
> +  SmallVector<unsigned, 8> VirtRegs;
> +
>   // Print explicitly defined operands on the left of an assignment syntax.
>   unsigned StartOp = 0, e = getNumOperands();
>   for (; StartOp < e && getOperand(StartOp).isReg() &&
> @@ -1250,6 +1256,9 @@
>        ++StartOp) {
>     if (StartOp != 0) OS << ", ";
>     getOperand(StartOp).print(OS, TM);
> +    unsigned Reg = getOperand(StartOp).getReg();
> +    if (Reg && TargetRegisterInfo::isVirtualRegister(Reg))
> +      VirtRegs.push_back(Reg);
>   }
> 
>   if (StartOp != 0)
> @@ -1264,6 +1273,10 @@
>   for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
>     const MachineOperand &MO = getOperand(i);
> 
> +    if (MO.isReg() && MO.getReg() &&
> +        TargetRegisterInfo::isVirtualRegister(MO.getReg()))
> +      VirtRegs.push_back(MO.getReg());
> +
>     // Omit call-clobbered registers which aren't used anywhere. This makes
>     // call instructions much less noisy on targets where calls clobber lots
>     // of registers. Don't rely on MO.isDead() because we may be called before
> @@ -1330,6 +1343,24 @@
>     }
>   }
> 
> +  // Print the regclass of any virtual registers encountered.
> +  if (MRI && !VirtRegs.empty()) {
> +    if (!HaveSemi) OS << ";"; HaveSemi = true;
> +    for (unsigned i = 0; i != VirtRegs.size(); ++i) {
> +      const TargetRegisterClass *RC = MRI->getRegClass(VirtRegs[i]);
> +      OS << " " << RC->getName() << ":%reg" << VirtRegs[i];
> +      for (unsigned j = i+1; j != VirtRegs.size();) {
> +        if (MRI->getRegClass(VirtRegs[j]) != RC) {
> +          ++j;
> +          continue;
> +        }
> +        if (VirtRegs[i] != VirtRegs[j])
> +          OS << "," << VirtRegs[j];
> +        VirtRegs.erase(VirtRegs.begin()+j);
> +      }
> +    }
> +  }
> +
>   if (!debugLoc.isUnknown() && MF) {
>     if (!HaveSemi) OS << ";";
>     OS << " dbg:";
> 
> 
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