[llvm-commits] [llvm] r109047 - in /llvm/trunk: lib/Target/ARM/ARMFastISel.cpp lib/Target/ARM/ARMISelLowering.cpp lib/Target/ARM/ARMISelLowering.h lib/Target/ARM/CMakeLists.txt lib/Target/ARM/Makefile test/CodeGen/ARM/fast-isel.ll
Evan Cheng
evan.cheng at apple.com
Mon Jul 26 11:27:30 PDT 2010
This is breaking ARM -O0. e.g.
unsigned FastEmit_ISD_Constant_MVT_i32_i(MVT RetVT, uint64_t imm0) {
if (RetVT.SimpleTy != MVT::i32)
return 0;
if ((!Subtarget->isThumb()) && (Subtarget->hasV6T2Ops())) {
return FastEmitInst_i(ARM::MOVi32imm, ARM::GPRRegisterClass, imm0);
}
if ((Subtarget->isThumb2())) {
=> return FastEmitInst_i(ARM::t2MOVi32imm, ARM::GPRRegisterClass, imm0);
}
return 0;
}
But FastISel::FastEmitInst_i isn't creating the right instructions for ARM since it doesn't add the default predicate operands. I'm going to disable fastisel for ARM for now.
Evan
On Jul 21, 2010, at 3:26 PM, Eric Christopher wrote:
> Author: echristo
> Date: Wed Jul 21 17:26:11 2010
> New Revision: 109047
>
> URL: http://llvm.org/viewvc/llvm-project?rev=109047&view=rev
> Log:
> Baby steps towards ARM fast-isel.
>
> Added:
> llvm/trunk/lib/Target/ARM/ARMFastISel.cpp
> llvm/trunk/test/CodeGen/ARM/fast-isel.ll
> Modified:
> llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
> llvm/trunk/lib/Target/ARM/ARMISelLowering.h
> llvm/trunk/lib/Target/ARM/CMakeLists.txt
> llvm/trunk/lib/Target/ARM/Makefile
>
> Added: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=109047&view=auto
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (added)
> +++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Wed Jul 21 17:26:11 2010
> @@ -0,0 +1,71 @@
> +//===-- ARMFastISel.cpp - ARM FastISel implementation ---------------------===//
> +//
> +// The LLVM Compiler Infrastructure
> +//
> +// This file is distributed under the University of Illinois Open Source
> +// License. See LICENSE.TXT for details.
> +//
> +//===----------------------------------------------------------------------===//
> +//
> +// This file defines the ARM-specific support for the FastISel class. Some
> +// of the target-specific code is generated by tablegen in the file
> +// ARMGenFastISel.inc, which is #included here.
> +//
> +//===----------------------------------------------------------------------===//
> +
> +#include "ARM.h"
> +#include "ARMRegisterInfo.h"
> +#include "ARMTargetMachine.h"
> +#include "ARMSubtarget.h"
> +#include "llvm/CallingConv.h"
> +#include "llvm/DerivedTypes.h"
> +#include "llvm/GlobalVariable.h"
> +#include "llvm/Instructions.h"
> +#include "llvm/IntrinsicInst.h"
> +#include "llvm/CodeGen/Analysis.h"
> +#include "llvm/CodeGen/FastISel.h"
> +#include "llvm/CodeGen/FunctionLoweringInfo.h"
> +#include "llvm/CodeGen/MachineConstantPool.h"
> +#include "llvm/CodeGen/MachineFrameInfo.h"
> +#include "llvm/CodeGen/MachineRegisterInfo.h"
> +#include "llvm/Support/CallSite.h"
> +#include "llvm/Support/ErrorHandling.h"
> +#include "llvm/Support/GetElementPtrTypeIterator.h"
> +#include "llvm/Target/TargetOptions.h"
> +using namespace llvm;
> +
> +namespace {
> +
> +class ARMFastISel : public FastISel {
> +
> + /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
> + /// make the right decision when generating code for different targets.
> + const ARMSubtarget *Subtarget;
> +
> + public:
> + explicit ARMFastISel(FunctionLoweringInfo &funcInfo) : FastISel(funcInfo) {
> + Subtarget = &TM.getSubtarget<ARMSubtarget>();
> + }
> +
> + virtual bool TargetSelectInstruction(const Instruction *I);
> +
> + #include "ARMGenFastISel.inc"
> +
> + };
> +
> +} // end anonymous namespace
> +
> +// #include "ARMGenCallingConv.inc"
> +
> +bool ARMFastISel::TargetSelectInstruction(const Instruction *I) {
> + switch (I->getOpcode()) {
> + default: break;
> + }
> + return false;
> +}
> +
> +namespace llvm {
> + llvm::FastISel *ARM::createFastISel(FunctionLoweringInfo &funcInfo) {
> + return new ARMFastISel(funcInfo);
> + }
> +}
>
> Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=109047&r1=109046&r2=109047&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Wed Jul 21 17:26:11 2010
> @@ -694,6 +694,12 @@
> return TargetLowering::getRegClassFor(VT);
> }
>
> +// Create a fast isel object.
> +FastISel *
> +ARMTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const {
> + return ARM::createFastISel(funcInfo);
> +}
> +
> /// getFunctionAlignment - Return the Log2 alignment of this function.
> unsigned ARMTargetLowering::getFunctionAlignment(const Function *F) const {
> return getTargetMachine().getSubtarget<ARMSubtarget>().isThumb() ? 1 : 2;
>
> Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.h?rev=109047&r1=109046&r2=109047&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMISelLowering.h (original)
> +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.h Wed Jul 21 17:26:11 2010
> @@ -17,6 +17,7 @@
>
> #include "ARMSubtarget.h"
> #include "llvm/Target/TargetLowering.h"
> +#include "llvm/CodeGen/FastISel.h"
> #include "llvm/CodeGen/SelectionDAG.h"
> #include "llvm/CodeGen/CallingConvLower.h"
> #include <vector>
> @@ -261,6 +262,10 @@
> /// getFunctionAlignment - Return the Log2 alignment of this function.
> virtual unsigned getFunctionAlignment(const Function *F) const;
>
> + /// createFastISel - This method returns a target specific FastISel object,
> + /// or null if the target does not support "fast" ISel.
> + virtual FastISel *createFastISel(FunctionLoweringInfo &funcInfo) const;
> +
> Sched::Preference getSchedulingPreference(SDNode *N) const;
>
> bool isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const;
> @@ -387,6 +392,10 @@
> unsigned BinOpcode) const;
>
> };
> +
> + namespace ARM {
> + FastISel *createFastISel(FunctionLoweringInfo &funcInfo);
> + }
> }
>
> #endif // ARMISELLOWERING_H
>
> Modified: llvm/trunk/lib/Target/ARM/CMakeLists.txt
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/CMakeLists.txt?rev=109047&r1=109046&r2=109047&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/CMakeLists.txt (original)
> +++ llvm/trunk/lib/Target/ARM/CMakeLists.txt Wed Jul 21 17:26:11 2010
> @@ -11,6 +11,7 @@
> tablegen(ARMGenCallingConv.inc -gen-callingconv)
> tablegen(ARMGenSubtarget.inc -gen-subtarget)
> tablegen(ARMGenEDInfo.inc -gen-enhanced-disassembly-info)
> +tablegen(ARMFastISel.inc -gen-fast-isel)
>
> add_llvm_target(ARMCodeGen
> ARMAsmPrinter.cpp
>
> Modified: llvm/trunk/lib/Target/ARM/Makefile
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Makefile?rev=109047&r1=109046&r2=109047&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/Makefile (original)
> +++ llvm/trunk/lib/Target/ARM/Makefile Wed Jul 21 17:26:11 2010
> @@ -17,7 +17,8 @@
> ARMGenInstrInfo.inc ARMGenAsmWriter.inc \
> ARMGenDAGISel.inc ARMGenSubtarget.inc \
> ARMGenCodeEmitter.inc ARMGenCallingConv.inc \
> - ARMGenDecoderTables.inc ARMGenEDInfo.inc
> + ARMGenDecoderTables.inc ARMGenEDInfo.inc \
> + ARMGenFastISel.inc
>
> DIRS = AsmPrinter AsmParser Disassembler TargetInfo
>
>
> Added: llvm/trunk/test/CodeGen/ARM/fast-isel.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fast-isel.ll?rev=109047&view=auto
> ==============================================================================
> --- llvm/trunk/test/CodeGen/ARM/fast-isel.ll (added)
> +++ llvm/trunk/test/CodeGen/ARM/fast-isel.ll Wed Jul 21 17:26:11 2010
> @@ -0,0 +1,15 @@
> +; RUN: llc < %s -fast-isel -fast-isel-abort -march=arm
> +
> +; Very basic fast-isel functionality.
> +
> +define i32 @add(i32 %a, i32 %b) nounwind ssp {
> +entry:
> + %a.addr = alloca i32, align 4
> + %b.addr = alloca i32, align 4
> + store i32 %a, i32* %a.addr
> + store i32 %b, i32* %b.addr
> + %tmp = load i32* %a.addr
> + %tmp1 = load i32* %b.addr
> + %add = add nsw i32 %tmp, %tmp1
> + ret i32 %add
> +}
>
>
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