[llvm-commits] [llvm] r109295 - in /llvm/trunk: lib/Target/X86/AsmParser/X86AsmParser.cpp lib/Target/X86/X86RegisterInfo.cpp lib/Target/X86/X86RegisterInfo.td test/MC/AsmParser/X86/x86_32-avx-encoding.s test/MC/AsmParser/X86/x86_32-encoding.s test/MC/AsmParser/X86/x86_64-avx-encoding.s test/MC/AsmParser/X86/x86_64-encoding.s
Bruno Cardoso Lopes
bruno.cardoso at gmail.com
Fri Jul 23 17:06:39 PDT 2010
Author: bruno
Date: Fri Jul 23 19:06:39 2010
New Revision: 109295
URL: http://llvm.org/viewvc/llvm-project?rev=109295&view=rev
Log:
Support x86 "eiz" and "riz" pseudo index registers in the assembler.
Modified:
llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp
llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
llvm/trunk/lib/Target/X86/X86RegisterInfo.td
llvm/trunk/test/MC/AsmParser/X86/x86_32-avx-encoding.s
llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s
llvm/trunk/test/MC/AsmParser/X86/x86_64-avx-encoding.s
llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s
Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=109295&r1=109294&r2=109295&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original)
+++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Fri Jul 23 19:06:39 2010
@@ -384,6 +384,12 @@
// validation later, so maybe there is no need for this here.
RegNo = MatchRegisterName(Tok.getString());
+ // FIXME: This should be done using Requires<In32BitMode> and
+ // Requires<In64BitMode> so "eiz" usage in 64-bit instructions
+ // can be also checked.
+ if (RegNo == X86::RIZ && !Is64Bit)
+ return Error(Tok.getLoc(), "riz register in 64-bit mode only");
+
// Parse %st(1) and "%st" as "%st(0)"
if (RegNo == 0 && Tok.getString() == "st") {
RegNo = X86::ST0;
@@ -459,6 +465,10 @@
unsigned RegNo;
SMLoc Start, End;
if (ParseRegister(RegNo, Start, End)) return 0;
+ if (RegNo == X86::EIZ || RegNo == X86::RIZ) {
+ Error(Start, "eiz and riz can only be used as index registers");
+ return 0;
+ }
// If this is a segment register followed by a ':', then this is the start
// of a memory reference, otherwise this is a normal register reference.
@@ -542,6 +552,10 @@
if (getLexer().is(AsmToken::Percent)) {
SMLoc L;
if (ParseRegister(BaseReg, L, L)) return 0;
+ if (BaseReg == X86::EIZ || BaseReg == X86::RIZ) {
+ Error(L, "eiz and riz can only be used as index registers");
+ return 0;
+ }
}
if (getLexer().is(AsmToken::Comma)) {
@@ -552,7 +566,7 @@
// correctly.
//
// Not that even though it would be completely consistent to support syntax
- // like "1(%eax,,1)", the assembler doesn't.
+ // like "1(%eax,,1)", the assembler doesn't. Use "eiz" or "riz" for this.
if (getLexer().is(AsmToken::Percent)) {
SMLoc L;
if (ParseRegister(IndexReg, L, L)) return 0;
Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp?rev=109295&r1=109294&r2=109295&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Fri Jul 23 19:06:39 2010
@@ -193,6 +193,12 @@
case X86::DR7:
return 7;
+ // Pseudo index registers are equivalent to a "none"
+ // scaled index (See Intel Manual 2A, table 2-3)
+ case X86::EIZ:
+ case X86::RIZ:
+ return 4;
+
default:
assert(isVirtualRegister(RegNo) && "Unknown physical register!");
llvm_unreachable("Register allocator hasn't allocated reg correctly yet!");
Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.td?rev=109295&r1=109294&r2=109295&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86RegisterInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86RegisterInfo.td Fri Jul 23 19:06:39 2010
@@ -241,6 +241,10 @@
def CR6 : Register<"cr6">;
def CR7 : Register<"cr7">;
def CR8 : Register<"cr8">;
+
+ // Pseudo index registers
+ def EIZ : Register<"eiz">;
+ def RIZ : Register<"riz">;
}
Modified: llvm/trunk/test/MC/AsmParser/X86/x86_32-avx-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_32-avx-encoding.s?rev=109295&r1=109294&r2=109295&view=diff
==============================================================================
--- llvm/trunk/test/MC/AsmParser/X86/x86_32-avx-encoding.s (original)
+++ llvm/trunk/test/MC/AsmParser/X86/x86_32-avx-encoding.s Fri Jul 23 19:06:39 2010
@@ -3235,3 +3235,7 @@
// CHECK: encoding: [0xc4,0xe2,0x7d,0x0e,0x10]
vtestps (%eax), %ymm2
+// CHECK: vblendvpd %ymm0, 57005(%eax,%eiz), %ymm1, %ymm2
+// CHECK: encoding: [0xc4,0xe3,0x75,0x4b,0x94,0x20,0xad,0xde,0x00,0x00,0x00]
+ vblendvpd %ymm0, 0xdead(%eax,%eiz), %ymm1, %ymm2
+
Modified: llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s?rev=109295&r1=109294&r2=109295&view=diff
==============================================================================
--- llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s (original)
+++ llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s Fri Jul 23 19:06:39 2010
@@ -10047,3 +10047,23 @@
// CHECK: encoding: [0xde,0x1d,0xed,0x7e,0x00,0x00]
ficomps 32493
+// CHECK: movl 57005(,%eiz), %ebx
+// CHECK: encoding: [0x8b,0x1c,0x25,0xad,0xde,0x00,0x00]
+ movl 57005(,%eiz), %ebx
+
+// CHECK: movl 48879(,%eiz), %eax
+// CHECK: encoding: [0x8b,0x04,0x25,0xef,0xbe,0x00,0x00]
+ movl 48879(,%eiz), %eax
+
+// CHECK: movl -4(,%eiz,8), %eax
+// CHECK: encoding: [0x8b,0x04,0xe5,0xfc,0xff,0xff,0xff]
+ movl -4(,%eiz,8), %eax
+
+// CHECK: movl (%ecx,%eiz), %eax
+// CHECK: encoding: [0x8b,0x04,0x21]
+ movl (%ecx,%eiz), %eax
+
+// CHECK: movl (%ecx,%eiz,8), %eax
+// CHECK: encoding: [0x8b,0x04,0xe1]
+ movl (%ecx,%eiz,8), %eax
+
Modified: llvm/trunk/test/MC/AsmParser/X86/x86_64-avx-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_64-avx-encoding.s?rev=109295&r1=109294&r2=109295&view=diff
==============================================================================
--- llvm/trunk/test/MC/AsmParser/X86/x86_64-avx-encoding.s (original)
+++ llvm/trunk/test/MC/AsmParser/X86/x86_64-avx-encoding.s Fri Jul 23 19:06:39 2010
@@ -3312,3 +3312,7 @@
// CHECK: encoding: [0xc5,0xf9,0xd7,0xcc]
vpmovmskb %xmm4, %rcx
+// CHECK: vblendvpd %ymm11, 57005(%rax,%riz), %ymm12, %ymm13
+// CHECK: encoding: [0xc4,0x63,0x1d,0x4b,0xac,0x20,0xad,0xde,0x00,0x00,0xb0]
+ vblendvpd %ymm11, 0xdead(%rax,%riz), %ymm12, %ymm13
+
Modified: llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s?rev=109295&r1=109294&r2=109295&view=diff
==============================================================================
--- llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s (original)
+++ llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s Fri Jul 23 19:06:39 2010
@@ -120,3 +120,23 @@
// CHECK: fixup A - offset: 5, value: CPI1_0-4
pshufb CPI1_0(%rip), %xmm1
+// CHECK: movq 57005(,%riz), %rbx
+// CHECK: encoding: [0x48,0x8b,0x1c,0x25,0xad,0xde,0x00,0x00]
+ movq 57005(,%riz), %rbx
+
+// CHECK: movq 48879(,%riz), %rax
+// CHECK: encoding: [0x48,0x8b,0x04,0x25,0xef,0xbe,0x00,0x00]
+ movq 48879(,%riz), %rax
+
+// CHECK: movq -4(,%riz,8), %rax
+// CHECK: encoding: [0x48,0x8b,0x04,0xe5,0xfc,0xff,0xff,0xff]
+ movq -4(,%riz,8), %rax
+
+// CHECK: movq (%rcx,%riz), %rax
+// CHECK: encoding: [0x48,0x8b,0x04,0x21]
+ movq (%rcx,%riz), %rax
+
+// CHECK: movq (%rcx,%riz,8), %rax
+// CHECK: encoding: [0x48,0x8b,0x04,0xe1]
+ movq (%rcx,%riz,8), %rax
+
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