[llvm-commits] [llvm] r109002 - in /llvm/trunk: lib/Target/X86/X86InstrSSE.td lib/Target/X86/X86MCCodeEmitter.cpp test/MC/AsmParser/X86/x86_32-encoding.s

[Bruno Cardoso Lopes]

Author: bruno
Date: Wed Jul 21 03:56:24 2010
New Revision: 109002

URL: http://llvm.org/viewvc/llvm-project?rev=109002&view=rev
Log:
Add AVX only vzeroall and vzeroupper instructions

Modified:
    llvm/trunk/lib/Target/X86/X86InstrSSE.td
    llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp
    llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=109002&r1=109001&r2=109002&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Wed Jul 21 03:56:24 2010
@@ -5076,4 +5076,10 @@
           "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
           []>, VEX_4V;
 
+// Zero All YMM registers
+def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall", []>, VEX, VEX_L;
+
+// Zero Upper bits of YMM registers
+def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper", []>, VEX;
+
 } // isAsmParserOnly

Modified: llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp?rev=109002&r1=109001&r2=109002&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp Wed Jul 21 03:56:24 2010
@@ -514,7 +514,10 @@
         VEX_X = 0x0;
     }
     break;
-  default: // MRMDestReg, MRM0r-MRM7r
+  default: // MRMDestReg, MRM0r-MRM7r, RawFrm
+    if (!MI.getNumOperands())
+      break;
+
     if (MI.getOperand(CurOp).isReg() &&
         X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
       VEX_B = 0;
@@ -530,7 +533,6 @@
         VEX_R = 0x0;
     }
     break;
-    assert(0 && "Not implemented!");
   }
 
   // Emit segment override opcode prefix as needed.

Modified: llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s?rev=109002&r1=109001&r2=109002&view=diff
==============================================================================
--- llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s (original)
+++ llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s Wed Jul 21 03:56:24 2010
@@ -13134,3 +13134,11 @@
 // CHECK: encoding: [0xc4,0xe3,0x55,0x06,0x08,0x07]
           vperm2f128  $7, (%eax), %ymm5, %ymm1
 
+// CHECK: vzeroall
+// CHECK: encoding: [0xc5,0xfc,0x77]
+          vzeroall
+
+// CHECK: vzeroupper
+// CHECK: encoding: [0xc5,0xf8,0x77]
+          vzeroupper
+