[llvm-commits] [patch] Fix calling convention on ARM if vfp2+ is enabled
deeppatel1987 at gmail.com
Tue Jul 20 17:18:44 PDT 2010
Nevermind, I see the test case in the patch.
This looks good to me. Sorry I missed this case.
On Tue, Jul 20, 2010 at 10:41 PM, Sandeep Patel <deeppatel1987 at gmail.com> wrote:
> I think this is what test/CodeGen/ARM/arguments.ll and
> arguments_f64_backfill.ll are testing.
> Can you provide a test that shows the case you think is incorrect?
> On Tue, Jul 20, 2010 at 10:29 PM, Rafael Espindola <espindola at google.com> wrote:
>> If vfp2 or newer is enabled, f64 is legal and we have to shadow r1
>> when a double is assigned to r2. This was already handle correctly
>> when f64 was being split, this patch adds the case where it is legal.
>> I changed which registers are "shadowed". My understanding is that
>> when a f64 is assigned to r2/r3, register r1 is the one shadowed.
>> Registers r2 and r3 are simply used. That is the meaning used on the
>> .td file. Should I change the .td?
>> Rafael Ávila de Espíndola
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu
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