[llvm-commits] [patch] Fix calling convention on ARM if vfp2+ is enabled

[Rafael Espindola]

If vfp2 or newer is enabled, f64 is legal and we have to shadow r1
when a double is assigned to r2. This was already handle correctly
when f64 was being split, this patch adds the case where it is legal.

I changed which registers are "shadowed". My understanding is that
when a f64 is assigned to r2/r3, register r1 is the one shadowed.
Registers r2 and r3 are simply used. That is the meaning used on the
.td file. Should I change the .td?

Cheers,
-- 
Rafael Ávila de Espíndola
-------------- next part --------------
A non-text attachment was scrubbed...
Name: cc.patch
Type: text/x-patch
Size: 2541 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20100720/a53db593/attachment.bin>