[llvm-commits] [llvm] r108328 - /llvm/trunk/lib/Target/ARM/README.txt

[Jim Grosbach]

Agreed. I'm looking at doing something about this. I don't think it'll be too horrible.

-Jim

On Jul 14, 2010, at 9:52 AM, Chris Lattner wrote:

> Wow, nice catch.  The thumb2 code in particular is really terrible, and this pattern occurs all the time for bitfield insertion.
> 
> -Chris
> 
> On Jul 13, 2010, at 11:58 PM, Eli Friedman wrote:
> 
>> Author: efriedma
>> Date: Wed Jul 14 01:58:26 2010
>> New Revision: 108328
>> 
>> URL: http://llvm.org/viewvc/llvm-project?rev=108328&view=rev
>> Log:
>> A couple potential optimizations inspired by comment 4 in PR6773.
>> 
>> 
>> Modified:
>>   llvm/trunk/lib/Target/ARM/README.txt
>> 
>> Modified: llvm/trunk/lib/Target/ARM/README.txt
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/README.txt?rev=108328&r1=108327&r2=108328&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/ARM/README.txt (original)
>> +++ llvm/trunk/lib/Target/ARM/README.txt Wed Jul 14 01:58:26 2010
>> @@ -590,3 +590,44 @@
>> associated with the comparison. Perhaps a pseudo-instruction for the comparison,
>> with a post-codegen pass to clean up and handle the condition codes?
>> See PR5694 for testcase.
>> +
>> +//===---------------------------------------------------------------------===//
>> +
>> +Given the following on armv5:
>> +int test1(int A, int B) {
>> +  return (A&-8388481)|(B&8388480);
>> +}
>> +
>> +We currently generate:
>> +	ldr	r2, .LCPI0_0
>> +	and	r0, r0, r2
>> +	ldr	r2, .LCPI0_1
>> +	and	r1, r1, r2
>> +	orr	r0, r1, r0
>> +	bx	lr
>> +
>> +We should be able to replace the second ldr+and with a bic (i.e. reuse the
>> +constant which was already loaded).  Not sure what's necessary to do that.
>> +
>> +//===---------------------------------------------------------------------===//
>> +
>> +Given the following on ARMv7:
>> +int test1(int A, int B) {
>> +  return (A&-8388481)|(B&8388480);
>> +}
>> +
>> +We currently generate:
>> +	bfc	r0, #7, #16
>> +	movw	r2, #:lower16:8388480
>> +	movt	r2, #:upper16:8388480
>> +	and	r1, r1, r2
>> +	orr	r0, r1, r0
>> +	bx	lr
>> +
>> +The following is much shorter:
>> +	lsr	r1, r1, #7
>> +	bfi	r0, r1, #7, #16
>> +	bx	lr
>> +
>> +
>> +//===---------------------------------------------------------------------===//
>> 
>> 
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