[llvm-commits] [llvm] r108099 - in /llvm/trunk/lib/Target: ARM/ARMBaseInstrInfo.cpp ARM/ARMBaseInstrInfo.h ARM/Thumb1InstrInfo.cpp ARM/Thumb1InstrInfo.h Alpha/AlphaInstrInfo.cpp Alpha/AlphaInstrInfo.h CellSPU/SPUInstrInfo.cpp CellSPU/SPUInstrInfo.h MBlaze/MBlazeInstrInfo.cpp MBlaze/MBlazeInstrInfo.h Mips/MipsInstrInfo.cpp Mips/MipsInstrInfo.h PowerPC/PPCInstrInfo.cpp PowerPC/PPCInstrInfo.h Sparc/SparcInstrInfo.cpp Sparc/SparcInstrInfo.h
Chris Lattner
clattner at apple.com
Sun Jul 11 14:49:41 PDT 2010
On Jul 11, 2010, at 12:19 PM, Jakob Stoklund Olesen wrote:
> Author: stoklund
> Date: Sun Jul 11 14:19:13 2010
> New Revision: 108099
>
> URL: http://llvm.org/viewvc/llvm-project?rev=108099&view=rev
> Log:
> RISC architectures get their memory operand folding for free.
>
> The only folding these load/store architectures can do is converting COPY into a
> load or store, and the target independent part of foldMemoryOperand already
> knows how to do that.
Whee! Look at all the minuses!
-Chris
>
> Modified:
> llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
> llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h
> llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp
> llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.h
> llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp
> llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.h
> llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp
> llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.h
> llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.cpp
> llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.h
> llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp
> llvm/trunk/lib/Target/Mips/MipsInstrInfo.h
> llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp
> llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h
> llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp
> llvm/trunk/lib/Target/Sparc/SparcInstrInfo.h
>
> Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=108099&r1=108098&r2=108099&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Sun Jul 11 14:19:13 2010
> @@ -949,223 +949,6 @@
> return &*MIB;
> }
>
> -MachineInstr *ARMBaseInstrInfo::
> -foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
> - const SmallVectorImpl<unsigned> &Ops, int FI) const {
> - if (Ops.size() != 1) return NULL;
> -
> - unsigned OpNum = Ops[0];
> - unsigned Opc = MI->getOpcode();
> - MachineInstr *NewMI = NULL;
> - if (Opc == ARM::MOVr || Opc == ARM::t2MOVr) {
> - // If it is updating CPSR, then it cannot be folded.
> - if (MI->getOperand(4).getReg() == ARM::CPSR && !MI->getOperand(4).isDead())
> - return NULL;
> - unsigned Pred = MI->getOperand(2).getImm();
> - unsigned PredReg = MI->getOperand(3).getReg();
> - if (OpNum == 0) { // move -> store
> - unsigned SrcReg = MI->getOperand(1).getReg();
> - unsigned SrcSubReg = MI->getOperand(1).getSubReg();
> - bool isKill = MI->getOperand(1).isKill();
> - bool isUndef = MI->getOperand(1).isUndef();
> - if (Opc == ARM::MOVr)
> - NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::STR))
> - .addReg(SrcReg,
> - getKillRegState(isKill) | getUndefRegState(isUndef),
> - SrcSubReg)
> - .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
> - else // ARM::t2MOVr
> - NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2STRi12))
> - .addReg(SrcReg,
> - getKillRegState(isKill) | getUndefRegState(isUndef),
> - SrcSubReg)
> - .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
> - } else { // move -> load
> - unsigned DstReg = MI->getOperand(0).getReg();
> - unsigned DstSubReg = MI->getOperand(0).getSubReg();
> - bool isDead = MI->getOperand(0).isDead();
> - bool isUndef = MI->getOperand(0).isUndef();
> - if (Opc == ARM::MOVr)
> - NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::LDR))
> - .addReg(DstReg,
> - RegState::Define |
> - getDeadRegState(isDead) |
> - getUndefRegState(isUndef), DstSubReg)
> - .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
> - else // ARM::t2MOVr
> - NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2LDRi12))
> - .addReg(DstReg,
> - RegState::Define |
> - getDeadRegState(isDead) |
> - getUndefRegState(isUndef), DstSubReg)
> - .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
> - }
> - } else if (Opc == ARM::tMOVgpr2gpr ||
> - Opc == ARM::tMOVtgpr2gpr ||
> - Opc == ARM::tMOVgpr2tgpr) {
> - if (OpNum == 0) { // move -> store
> - unsigned SrcReg = MI->getOperand(1).getReg();
> - unsigned SrcSubReg = MI->getOperand(1).getSubReg();
> - bool isKill = MI->getOperand(1).isKill();
> - bool isUndef = MI->getOperand(1).isUndef();
> - NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2STRi12))
> - .addReg(SrcReg,
> - getKillRegState(isKill) | getUndefRegState(isUndef),
> - SrcSubReg)
> - .addFrameIndex(FI).addImm(0).addImm(ARMCC::AL).addReg(0);
> - } else { // move -> load
> - unsigned DstReg = MI->getOperand(0).getReg();
> - unsigned DstSubReg = MI->getOperand(0).getSubReg();
> - bool isDead = MI->getOperand(0).isDead();
> - bool isUndef = MI->getOperand(0).isUndef();
> - NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2LDRi12))
> - .addReg(DstReg,
> - RegState::Define |
> - getDeadRegState(isDead) |
> - getUndefRegState(isUndef),
> - DstSubReg)
> - .addFrameIndex(FI).addImm(0).addImm(ARMCC::AL).addReg(0);
> - }
> - } else if (Opc == ARM::VMOVS) {
> - unsigned Pred = MI->getOperand(2).getImm();
> - unsigned PredReg = MI->getOperand(3).getReg();
> - if (OpNum == 0) { // move -> store
> - unsigned SrcReg = MI->getOperand(1).getReg();
> - unsigned SrcSubReg = MI->getOperand(1).getSubReg();
> - bool isKill = MI->getOperand(1).isKill();
> - bool isUndef = MI->getOperand(1).isUndef();
> - NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VSTRS))
> - .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef),
> - SrcSubReg)
> - .addFrameIndex(FI)
> - .addImm(0).addImm(Pred).addReg(PredReg);
> - } else { // move -> load
> - unsigned DstReg = MI->getOperand(0).getReg();
> - unsigned DstSubReg = MI->getOperand(0).getSubReg();
> - bool isDead = MI->getOperand(0).isDead();
> - bool isUndef = MI->getOperand(0).isUndef();
> - NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VLDRS))
> - .addReg(DstReg,
> - RegState::Define |
> - getDeadRegState(isDead) |
> - getUndefRegState(isUndef),
> - DstSubReg)
> - .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
> - }
> - } else if (Opc == ARM::VMOVD || Opc == ARM::VMOVDneon) {
> - unsigned Pred = MI->getOperand(2).getImm();
> - unsigned PredReg = MI->getOperand(3).getReg();
> - if (OpNum == 0) { // move -> store
> - unsigned SrcReg = MI->getOperand(1).getReg();
> - unsigned SrcSubReg = MI->getOperand(1).getSubReg();
> - bool isKill = MI->getOperand(1).isKill();
> - bool isUndef = MI->getOperand(1).isUndef();
> - NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VSTRD))
> - .addReg(SrcReg,
> - getKillRegState(isKill) | getUndefRegState(isUndef),
> - SrcSubReg)
> - .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
> - } else { // move -> load
> - unsigned DstReg = MI->getOperand(0).getReg();
> - unsigned DstSubReg = MI->getOperand(0).getSubReg();
> - bool isDead = MI->getOperand(0).isDead();
> - bool isUndef = MI->getOperand(0).isUndef();
> - NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VLDRD))
> - .addReg(DstReg,
> - RegState::Define |
> - getDeadRegState(isDead) |
> - getUndefRegState(isUndef),
> - DstSubReg)
> - .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
> - }
> - } else if (Opc == ARM::VMOVQ) {
> - MachineFrameInfo &MFI = *MF.getFrameInfo();
> - unsigned Pred = MI->getOperand(2).getImm();
> - unsigned PredReg = MI->getOperand(3).getReg();
> - if (OpNum == 0) { // move -> store
> - unsigned SrcReg = MI->getOperand(1).getReg();
> - unsigned SrcSubReg = MI->getOperand(1).getSubReg();
> - bool isKill = MI->getOperand(1).isKill();
> - bool isUndef = MI->getOperand(1).isUndef();
> - if (MFI.getObjectAlignment(FI) >= 16 &&
> - getRegisterInfo().canRealignStack(MF)) {
> - NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VST1q))
> - .addFrameIndex(FI).addImm(16)
> - .addReg(SrcReg,
> - getKillRegState(isKill) | getUndefRegState(isUndef),
> - SrcSubReg)
> - .addImm(Pred).addReg(PredReg);
> - } else {
> - NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VSTMQ))
> - .addReg(SrcReg,
> - getKillRegState(isKill) | getUndefRegState(isUndef),
> - SrcSubReg)
> - .addFrameIndex(FI).addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4))
> - .addImm(Pred).addReg(PredReg);
> - }
> - } else { // move -> load
> - unsigned DstReg = MI->getOperand(0).getReg();
> - unsigned DstSubReg = MI->getOperand(0).getSubReg();
> - bool isDead = MI->getOperand(0).isDead();
> - bool isUndef = MI->getOperand(0).isUndef();
> - if (MFI.getObjectAlignment(FI) >= 16 &&
> - getRegisterInfo().canRealignStack(MF)) {
> - NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VLD1q))
> - .addReg(DstReg,
> - RegState::Define |
> - getDeadRegState(isDead) |
> - getUndefRegState(isUndef),
> - DstSubReg)
> - .addFrameIndex(FI).addImm(16).addImm(Pred).addReg(PredReg);
> - } else {
> - NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::VLDMQ))
> - .addReg(DstReg,
> - RegState::Define |
> - getDeadRegState(isDead) |
> - getUndefRegState(isUndef),
> - DstSubReg)
> - .addFrameIndex(FI).addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4))
> - .addImm(Pred).addReg(PredReg);
> - }
> - }
> - }
> -
> - return NewMI;
> -}
> -
> -MachineInstr*
> -ARMBaseInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
> - MachineInstr* MI,
> - const SmallVectorImpl<unsigned> &Ops,
> - MachineInstr* LoadMI) const {
> - // FIXME
> - return 0;
> -}
> -
> -bool
> -ARMBaseInstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
> - const SmallVectorImpl<unsigned> &Ops) const {
> - if (Ops.size() != 1) return false;
> -
> - unsigned Opc = MI->getOpcode();
> - if (Opc == ARM::MOVr || Opc == ARM::t2MOVr) {
> - // If it is updating CPSR, then it cannot be folded.
> - return MI->getOperand(4).getReg() != ARM::CPSR ||
> - MI->getOperand(4).isDead();
> - } else if (Opc == ARM::tMOVgpr2gpr ||
> - Opc == ARM::tMOVtgpr2gpr ||
> - Opc == ARM::tMOVgpr2tgpr) {
> - return true;
> - } else if (Opc == ARM::VMOVS || Opc == ARM::VMOVD ||
> - Opc == ARM::VMOVDneon || Opc == ARM::VMOVQ) {
> - return true;
> - }
> -
> - // FIXME: VMOVQQ and VMOVQQQQ?
> -
> - return TargetInstrInfoImpl::canFoldMemoryOperand(MI, Ops);
> -}
> -
> /// Create a copy of a const pool value. Update CPI to the new index and return
> /// the label UID.
> static unsigned duplicateCPV(MachineFunction &MF, unsigned &CPI) {
>
> Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h?rev=108099&r1=108098&r2=108099&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h (original)
> +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h Sun Jul 11 14:19:13 2010
> @@ -296,19 +296,6 @@
> const MDNode *MDPtr,
> DebugLoc DL) const;
>
> - virtual bool canFoldMemoryOperand(const MachineInstr *MI,
> - const SmallVectorImpl<unsigned> &Ops) const;
> -
> - virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
> - MachineInstr* MI,
> - const SmallVectorImpl<unsigned> &Ops,
> - int FrameIndex) const;
> -
> - virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
> - MachineInstr* MI,
> - const SmallVectorImpl<unsigned> &Ops,
> - MachineInstr* LoadMI) const;
> -
> virtual void reMaterialize(MachineBasicBlock &MBB,
> MachineBasicBlock::iterator MI,
> unsigned DestReg, unsigned SubIdx,
>
> Modified: llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp?rev=108099&r1=108098&r2=108099&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp Sun Jul 11 14:19:13 2010
> @@ -53,39 +53,6 @@
> "Thumb1 can only copy GPR registers");
> }
>
> -bool Thumb1InstrInfo::
> -canFoldMemoryOperand(const MachineInstr *MI,
> - const SmallVectorImpl<unsigned> &Ops) const {
> - if (Ops.size() != 1) return false;
> -
> - unsigned OpNum = Ops[0];
> - unsigned Opc = MI->getOpcode();
> - switch (Opc) {
> - default: break;
> - case ARM::tMOVr:
> - case ARM::tMOVtgpr2gpr:
> - case ARM::tMOVgpr2tgpr:
> - case ARM::tMOVgpr2gpr: {
> - if (OpNum == 0) { // move -> store
> - unsigned SrcReg = MI->getOperand(1).getReg();
> - if (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
> - !isARMLowRegister(SrcReg))
> - // tSpill cannot take a high register operand.
> - return false;
> - } else { // move -> load
> - unsigned DstReg = MI->getOperand(0).getReg();
> - if (TargetRegisterInfo::isPhysicalRegister(DstReg) &&
> - !isARMLowRegister(DstReg))
> - // tRestore cannot target a high register operand.
> - return false;
> - }
> - return true;
> - }
> - }
> -
> - return false;
> -}
> -
> void Thumb1InstrInfo::
> storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
> unsigned SrcReg, bool isKill, int FI,
> @@ -214,46 +181,3 @@
>
> return true;
> }
> -
> -MachineInstr *Thumb1InstrInfo::
> -foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
> - const SmallVectorImpl<unsigned> &Ops, int FI) const {
> - if (Ops.size() != 1) return NULL;
> -
> - unsigned OpNum = Ops[0];
> - unsigned Opc = MI->getOpcode();
> - MachineInstr *NewMI = NULL;
> - switch (Opc) {
> - default: break;
> - case ARM::tMOVr:
> - case ARM::tMOVtgpr2gpr:
> - case ARM::tMOVgpr2tgpr:
> - case ARM::tMOVgpr2gpr: {
> - if (OpNum == 0) { // move -> store
> - unsigned SrcReg = MI->getOperand(1).getReg();
> - bool isKill = MI->getOperand(1).isKill();
> - if (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
> - !isARMLowRegister(SrcReg))
> - // tSpill cannot take a high register operand.
> - break;
> - NewMI = AddDefaultPred(BuildMI(MF, MI->getDebugLoc(), get(ARM::tSpill))
> - .addReg(SrcReg, getKillRegState(isKill))
> - .addFrameIndex(FI).addImm(0));
> - } else { // move -> load
> - unsigned DstReg = MI->getOperand(0).getReg();
> - if (TargetRegisterInfo::isPhysicalRegister(DstReg) &&
> - !isARMLowRegister(DstReg))
> - // tRestore cannot target a high register operand.
> - break;
> - bool isDead = MI->getOperand(0).isDead();
> - NewMI = AddDefaultPred(BuildMI(MF, MI->getDebugLoc(), get(ARM::tRestore))
> - .addReg(DstReg,
> - RegState::Define | getDeadRegState(isDead))
> - .addFrameIndex(FI).addImm(0));
> - }
> - break;
> - }
> - }
> -
> - return NewMI;
> -}
>
> Modified: llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.h?rev=108099&r1=108098&r2=108099&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.h (original)
> +++ llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.h Sun Jul 11 14:19:13 2010
> @@ -62,20 +62,6 @@
> const TargetRegisterClass *RC,
> const TargetRegisterInfo *TRI) const;
>
> - bool canFoldMemoryOperand(const MachineInstr *MI,
> - const SmallVectorImpl<unsigned> &Ops) const;
> -
> - MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
> - MachineInstr* MI,
> - const SmallVectorImpl<unsigned> &Ops,
> - int FrameIndex) const;
> -
> - MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
> - MachineInstr* MI,
> - const SmallVectorImpl<unsigned> &Ops,
> - MachineInstr* LoadMI) const {
> - return 0;
> - }
> };
> }
>
>
> Modified: llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp?rev=108099&r1=108098&r2=108099&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp (original)
> +++ llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp Sun Jul 11 14:19:13 2010
> @@ -215,51 +215,6 @@
> llvm_unreachable("Unhandled register class");
> }
>
> -MachineInstr *AlphaInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
> - MachineInstr *MI,
> - const SmallVectorImpl<unsigned> &Ops,
> - int FrameIndex) const {
> - if (Ops.size() != 1) return NULL;
> -
> - // Make sure this is a reg-reg copy.
> - unsigned Opc = MI->getOpcode();
> -
> - MachineInstr *NewMI = NULL;
> - switch(Opc) {
> - default:
> - break;
> - case Alpha::BISr:
> - case Alpha::CPYSS:
> - case Alpha::CPYST:
> - if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) {
> - if (Ops[0] == 0) { // move -> store
> - unsigned InReg = MI->getOperand(1).getReg();
> - bool isKill = MI->getOperand(1).isKill();
> - bool isUndef = MI->getOperand(1).isUndef();
> - Opc = (Opc == Alpha::BISr) ? Alpha::STQ :
> - ((Opc == Alpha::CPYSS) ? Alpha::STS : Alpha::STT);
> - NewMI = BuildMI(MF, MI->getDebugLoc(), get(Opc))
> - .addReg(InReg, getKillRegState(isKill) | getUndefRegState(isUndef))
> - .addFrameIndex(FrameIndex)
> - .addReg(Alpha::F31);
> - } else { // load -> move
> - unsigned OutReg = MI->getOperand(0).getReg();
> - bool isDead = MI->getOperand(0).isDead();
> - bool isUndef = MI->getOperand(0).isUndef();
> - Opc = (Opc == Alpha::BISr) ? Alpha::LDQ :
> - ((Opc == Alpha::CPYSS) ? Alpha::LDS : Alpha::LDT);
> - NewMI = BuildMI(MF, MI->getDebugLoc(), get(Opc))
> - .addReg(OutReg, RegState::Define | getDeadRegState(isDead) |
> - getUndefRegState(isUndef))
> - .addFrameIndex(FrameIndex)
> - .addReg(Alpha::F31);
> - }
> - }
> - break;
> - }
> - return NewMI;
> -}
> -
> static unsigned AlphaRevCondCode(unsigned Opcode) {
> switch (Opcode) {
> case Alpha::BEQ: return Alpha::BNE;
>
> Modified: llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.h?rev=108099&r1=108098&r2=108099&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.h (original)
> +++ llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.h Sun Jul 11 14:19:13 2010
> @@ -61,18 +61,6 @@
> const TargetRegisterClass *RC,
> const TargetRegisterInfo *TRI) const;
>
> - virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
> - MachineInstr* MI,
> - const SmallVectorImpl<unsigned> &Ops,
> - int FrameIndex) const;
> -
> - virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
> - MachineInstr* MI,
> - const SmallVectorImpl<unsigned> &Ops,
> - MachineInstr* LoadMI) const {
> - return 0;
> - }
> -
> bool AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
> MachineBasicBlock *&FBB,
> SmallVectorImpl<MachineOperand> &Cond,
>
> Modified: llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp?rev=108099&r1=108098&r2=108099&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp (original)
> +++ llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp Sun Jul 11 14:19:13 2010
> @@ -332,88 +332,6 @@
> addFrameReference(BuildMI(MBB, MI, DL, get(opc), DestReg), FrameIdx);
> }
>
> -//! Return true if the specified load or store can be folded
> -bool
> -SPUInstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
> - const SmallVectorImpl<unsigned> &Ops) const {
> - if (Ops.size() != 1) return false;
> -
> - // Make sure this is a reg-reg copy.
> - unsigned Opc = MI->getOpcode();
> -
> - switch (Opc) {
> - case SPU::ORv16i8:
> - case SPU::ORv8i16:
> - case SPU::ORv4i32:
> - case SPU::ORv2i64:
> - case SPU::ORr8:
> - case SPU::ORr16:
> - case SPU::ORr32:
> - case SPU::ORr64:
> - case SPU::ORf32:
> - case SPU::ORf64:
> - if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
> - return true;
> - break;
> - }
> -
> - return false;
> -}
> -
> -/// foldMemoryOperand - SPU, like PPC, can only fold spills into
> -/// copy instructions, turning them into load/store instructions.
> -MachineInstr *
> -SPUInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
> - MachineInstr *MI,
> - const SmallVectorImpl<unsigned> &Ops,
> - int FrameIndex) const
> -{
> - if (Ops.size() != 1) return 0;
> -
> - unsigned OpNum = Ops[0];
> - unsigned Opc = MI->getOpcode();
> - MachineInstr *NewMI = 0;
> -
> - switch (Opc) {
> - case SPU::ORv16i8:
> - case SPU::ORv8i16:
> - case SPU::ORv4i32:
> - case SPU::ORv2i64:
> - case SPU::ORr8:
> - case SPU::ORr16:
> - case SPU::ORr32:
> - case SPU::ORr64:
> - case SPU::ORf32:
> - case SPU::ORf64:
> - if (OpNum == 0) { // move -> store
> - unsigned InReg = MI->getOperand(1).getReg();
> - bool isKill = MI->getOperand(1).isKill();
> - bool isUndef = MI->getOperand(1).isUndef();
> - if (FrameIndex < SPUFrameInfo::maxFrameOffset()) {
> - MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(),
> - get(SPU::STQDr32));
> -
> - MIB.addReg(InReg, getKillRegState(isKill) | getUndefRegState(isUndef));
> - NewMI = addFrameReference(MIB, FrameIndex);
> - }
> - } else { // move -> load
> - unsigned OutReg = MI->getOperand(0).getReg();
> - bool isDead = MI->getOperand(0).isDead();
> - bool isUndef = MI->getOperand(0).isUndef();
> - MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc));
> -
> - MIB.addReg(OutReg, RegState::Define | getDeadRegState(isDead) |
> - getUndefRegState(isUndef));
> - Opc = (FrameIndex < SPUFrameInfo::maxFrameOffset())
> - ? SPU::STQDr32 : SPU::STQXr32;
> - NewMI = addFrameReference(MIB, FrameIndex);
> - break;
> - }
> - }
> -
> - return NewMI;
> -}
> -
> //! Branch analysis
> /*!
> \note This code was kiped from PPC. There may be more branch analysis for
>
> Modified: llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.h?rev=108099&r1=108098&r2=108099&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.h (original)
> +++ llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.h Sun Jul 11 14:19:13 2010
> @@ -23,19 +23,6 @@
> class SPUInstrInfo : public TargetInstrInfoImpl {
> SPUTargetMachine &TM;
> const SPURegisterInfo RI;
> - protected:
> - virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
> - MachineInstr* MI,
> - const SmallVectorImpl<unsigned> &Ops,
> - int FrameIndex) const;
> -
> - virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
> - MachineInstr* MI,
> - const SmallVectorImpl<unsigned> &Ops,
> - MachineInstr* LoadMI) const {
> - return 0;
> - }
> -
> public:
> explicit SPUInstrInfo(SPUTargetMachine &tm);
>
> @@ -75,11 +62,6 @@
> const TargetRegisterClass *RC,
> const TargetRegisterInfo *TRI) const;
>
> - //! Return true if the specified load or store can be folded
> - virtual
> - bool canFoldMemoryOperand(const MachineInstr *MI,
> - const SmallVectorImpl<unsigned> &Ops) const;
> -
> //! Reverses a branch's condition, returning false on success.
> virtual
> bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
>
> Modified: llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.cpp?rev=108099&r1=108098&r2=108099&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.cpp (original)
> +++ llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.cpp Sun Jul 11 14:19:13 2010
> @@ -139,44 +139,6 @@
> .addImm(0).addFrameIndex(FI);
> }
>
> -MachineInstr *MBlazeInstrInfo::
> -foldMemoryOperandImpl(MachineFunction &MF,
> - MachineInstr* MI,
> - const SmallVectorImpl<unsigned> &Ops, int FI) const {
> - if (Ops.size() != 1) return NULL;
> -
> - MachineInstr *NewMI = NULL;
> -
> - switch (MI->getOpcode()) {
> - case MBlaze::OR:
> - case MBlaze::ADD:
> - if ((MI->getOperand(0).isReg()) &&
> - (MI->getOperand(2).isReg()) &&
> - (MI->getOperand(2).getReg() == MBlaze::R0) &&
> - (MI->getOperand(1).isReg())) {
> - if (Ops[0] == 0) { // COPY -> STORE
> - unsigned SrcReg = MI->getOperand(1).getReg();
> - bool isKill = MI->getOperand(1).isKill();
> - bool isUndef = MI->getOperand(1).isUndef();
> - NewMI = BuildMI(MF, MI->getDebugLoc(), get(MBlaze::SW))
> - .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
> - .addImm(0).addFrameIndex(FI);
> - } else { // COPY -> LOAD
> - unsigned DstReg = MI->getOperand(0).getReg();
> - bool isDead = MI->getOperand(0).isDead();
> - bool isUndef = MI->getOperand(0).isUndef();
> - NewMI = BuildMI(MF, MI->getDebugLoc(), get(MBlaze::LW))
> - .addReg(DstReg, RegState::Define | getDeadRegState(isDead) |
> - getUndefRegState(isUndef))
> - .addImm(0).addFrameIndex(FI);
> - }
> - }
> - break;
> - }
> -
> - return NewMI;
> -}
> -
> //===----------------------------------------------------------------------===//
> // Branch Analysis
> //===----------------------------------------------------------------------===//
>
> Modified: llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.h?rev=108099&r1=108098&r2=108099&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.h (original)
> +++ llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.h Sun Jul 11 14:19:13 2010
> @@ -216,18 +216,6 @@
> const TargetRegisterClass *RC,
> const TargetRegisterInfo *TRI) const;
>
> - virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
> - MachineInstr* MI,
> - const SmallVectorImpl<unsigned> &Ops,
> - int FrameIndex) const;
> -
> - virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
> - MachineInstr* MI,
> - const SmallVectorImpl<unsigned> &Ops,
> - MachineInstr* LoadMI) const {
> - return 0;
> - }
> -
> /// Insert nop instruction when hazard condition is found
> virtual void insertNoop(MachineBasicBlock &MBB,
> MachineBasicBlock::iterator MI) const;
>
> Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp?rev=108099&r1=108098&r2=108099&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp (original)
> +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp Sun Jul 11 14:19:13 2010
> @@ -261,80 +261,6 @@
> llvm_unreachable("Register class not handled!");
> }
>
> -MachineInstr *MipsInstrInfo::
> -foldMemoryOperandImpl(MachineFunction &MF,
> - MachineInstr* MI,
> - const SmallVectorImpl<unsigned> &Ops, int FI) const
> -{
> - if (Ops.size() != 1) return NULL;
> -
> - MachineInstr *NewMI = NULL;
> -
> - switch (MI->getOpcode()) {
> - case Mips::ADDu:
> - if ((MI->getOperand(0).isReg()) &&
> - (MI->getOperand(1).isReg()) &&
> - (MI->getOperand(1).getReg() == Mips::ZERO) &&
> - (MI->getOperand(2).isReg())) {
> - if (Ops[0] == 0) { // COPY -> STORE
> - unsigned SrcReg = MI->getOperand(2).getReg();
> - bool isKill = MI->getOperand(2).isKill();
> - bool isUndef = MI->getOperand(2).isUndef();
> - NewMI = BuildMI(MF, MI->getDebugLoc(), get(Mips::SW))
> - .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
> - .addImm(0).addFrameIndex(FI);
> - } else { // COPY -> LOAD
> - unsigned DstReg = MI->getOperand(0).getReg();
> - bool isDead = MI->getOperand(0).isDead();
> - bool isUndef = MI->getOperand(0).isUndef();
> - NewMI = BuildMI(MF, MI->getDebugLoc(), get(Mips::LW))
> - .addReg(DstReg, RegState::Define | getDeadRegState(isDead) |
> - getUndefRegState(isUndef))
> - .addImm(0).addFrameIndex(FI);
> - }
> - }
> - break;
> - case Mips::FMOV_S32:
> - case Mips::FMOV_D32:
> - if ((MI->getOperand(0).isReg()) &&
> - (MI->getOperand(1).isReg())) {
> - const TargetRegisterClass
> - *RC = RI.getRegClass(MI->getOperand(0).getReg());
> - unsigned StoreOpc, LoadOpc;
> - bool IsMips1 = TM.getSubtarget<MipsSubtarget>().isMips1();
> -
> - if (RC == Mips::FGR32RegisterClass) {
> - LoadOpc = Mips::LWC1; StoreOpc = Mips::SWC1;
> - } else {
> - assert(RC == Mips::AFGR64RegisterClass);
> - // Mips1 doesn't have ldc/sdc instructions.
> - if (IsMips1) break;
> - LoadOpc = Mips::LDC1; StoreOpc = Mips::SDC1;
> - }
> -
> - if (Ops[0] == 0) { // COPY -> STORE
> - unsigned SrcReg = MI->getOperand(1).getReg();
> - bool isKill = MI->getOperand(1).isKill();
> - bool isUndef = MI->getOperand(2).isUndef();
> - NewMI = BuildMI(MF, MI->getDebugLoc(), get(StoreOpc))
> - .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
> - .addImm(0).addFrameIndex(FI) ;
> - } else { // COPY -> LOAD
> - unsigned DstReg = MI->getOperand(0).getReg();
> - bool isDead = MI->getOperand(0).isDead();
> - bool isUndef = MI->getOperand(0).isUndef();
> - NewMI = BuildMI(MF, MI->getDebugLoc(), get(LoadOpc))
> - .addReg(DstReg, RegState::Define | getDeadRegState(isDead) |
> - getUndefRegState(isUndef))
> - .addImm(0).addFrameIndex(FI);
> - }
> - }
> - break;
> - }
> -
> - return NewMI;
> -}
> -
> //===----------------------------------------------------------------------===//
> // Branch Analysis
> //===----------------------------------------------------------------------===//
>
> Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.h?rev=108099&r1=108098&r2=108099&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.h (original)
> +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.h Sun Jul 11 14:19:13 2010
> @@ -222,18 +222,6 @@
> const TargetRegisterClass *RC,
> const TargetRegisterInfo *TRI) const;
>
> - virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
> - MachineInstr* MI,
> - const SmallVectorImpl<unsigned> &Ops,
> - int FrameIndex) const;
> -
> - virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
> - MachineInstr* MI,
> - const SmallVectorImpl<unsigned> &Ops,
> - MachineInstr* LoadMI) const {
> - return 0;
> - }
> -
> virtual
> bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
>
>
> Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp?rev=108099&r1=108098&r2=108099&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp (original)
> +++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp Sun Jul 11 14:19:13 2010
> @@ -649,121 +649,6 @@
> return &*MIB;
> }
>
> -/// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into
> -/// copy instructions, turning them into load/store instructions.
> -MachineInstr *PPCInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
> - MachineInstr *MI,
> - const SmallVectorImpl<unsigned> &Ops,
> - int FrameIndex) const {
> - if (Ops.size() != 1) return NULL;
> -
> - // Make sure this is a reg-reg copy. Note that we can't handle MCRF, because
> - // it takes more than one instruction to store it.
> - unsigned Opc = MI->getOpcode();
> - unsigned OpNum = Ops[0];
> -
> - MachineInstr *NewMI = NULL;
> - if ((Opc == PPC::OR &&
> - MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
> - if (OpNum == 0) { // move -> store
> - unsigned InReg = MI->getOperand(1).getReg();
> - bool isKill = MI->getOperand(1).isKill();
> - bool isUndef = MI->getOperand(1).isUndef();
> - NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::STW))
> - .addReg(InReg,
> - getKillRegState(isKill) |
> - getUndefRegState(isUndef)),
> - FrameIndex);
> - } else { // move -> load
> - unsigned OutReg = MI->getOperand(0).getReg();
> - bool isDead = MI->getOperand(0).isDead();
> - bool isUndef = MI->getOperand(0).isUndef();
> - NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::LWZ))
> - .addReg(OutReg,
> - RegState::Define |
> - getDeadRegState(isDead) |
> - getUndefRegState(isUndef)),
> - FrameIndex);
> - }
> - } else if ((Opc == PPC::OR8 &&
> - MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
> - if (OpNum == 0) { // move -> store
> - unsigned InReg = MI->getOperand(1).getReg();
> - bool isKill = MI->getOperand(1).isKill();
> - bool isUndef = MI->getOperand(1).isUndef();
> - NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::STD))
> - .addReg(InReg,
> - getKillRegState(isKill) |
> - getUndefRegState(isUndef)),
> - FrameIndex);
> - } else { // move -> load
> - unsigned OutReg = MI->getOperand(0).getReg();
> - bool isDead = MI->getOperand(0).isDead();
> - bool isUndef = MI->getOperand(0).isUndef();
> - NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::LD))
> - .addReg(OutReg,
> - RegState::Define |
> - getDeadRegState(isDead) |
> - getUndefRegState(isUndef)),
> - FrameIndex);
> - }
> - } else if (Opc == PPC::FMR || Opc == PPC::FMRSD) {
> - // The register may be F4RC or F8RC, and that determines the memory op.
> - unsigned OrigReg = MI->getOperand(OpNum).getReg();
> - // We cannot tell the register class from a physreg alone.
> - if (TargetRegisterInfo::isPhysicalRegister(OrigReg))
> - return NULL;
> - const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(OrigReg);
> - const bool is64 = RC == PPC::F8RCRegisterClass;
> -
> - if (OpNum == 0) { // move -> store
> - unsigned InReg = MI->getOperand(1).getReg();
> - bool isKill = MI->getOperand(1).isKill();
> - bool isUndef = MI->getOperand(1).isUndef();
> - NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(),
> - get(is64 ? PPC::STFD : PPC::STFS))
> - .addReg(InReg,
> - getKillRegState(isKill) |
> - getUndefRegState(isUndef)),
> - FrameIndex);
> - } else { // move -> load
> - unsigned OutReg = MI->getOperand(0).getReg();
> - bool isDead = MI->getOperand(0).isDead();
> - bool isUndef = MI->getOperand(0).isUndef();
> - NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(),
> - get(is64 ? PPC::LFD : PPC::LFS))
> - .addReg(OutReg,
> - RegState::Define |
> - getDeadRegState(isDead) |
> - getUndefRegState(isUndef)),
> - FrameIndex);
> - }
> - }
> -
> - return NewMI;
> -}
> -
> -bool PPCInstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
> - const SmallVectorImpl<unsigned> &Ops) const {
> - if (Ops.size() != 1) return false;
> -
> - // Make sure this is a reg-reg copy. Note that we can't handle MCRF, because
> - // it takes more than one instruction to store it.
> - unsigned Opc = MI->getOpcode();
> -
> - if ((Opc == PPC::OR &&
> - MI->getOperand(1).getReg() == MI->getOperand(2).getReg()))
> - return true;
> - else if ((Opc == PPC::OR8 &&
> - MI->getOperand(1).getReg() == MI->getOperand(2).getReg()))
> - return true;
> - else if (Opc == PPC::FMR || Opc == PPC::FMRSD)
> - return true;
> -
> - return false;
> -}
> -
> -
> bool PPCInstrInfo::
> ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
> assert(Cond.size() == 2 && "Invalid PPC branch opcode!");
>
> Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h?rev=108099&r1=108098&r2=108099&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h (original)
> +++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h Sun Jul 11 14:19:13 2010
> @@ -134,23 +134,6 @@
> const MDNode *MDPtr,
> DebugLoc DL) const;
>
> - /// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into
> - /// copy instructions, turning them into load/store instructions.
> - virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
> - MachineInstr* MI,
> - const SmallVectorImpl<unsigned> &Ops,
> - int FrameIndex) const;
> -
> - virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
> - MachineInstr* MI,
> - const SmallVectorImpl<unsigned> &Ops,
> - MachineInstr* LoadMI) const {
> - return 0;
> - }
> -
> - virtual bool canFoldMemoryOperand(const MachineInstr *MI,
> - const SmallVectorImpl<unsigned> &Ops) const;
> -
> virtual
> bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
>
>
> Modified: llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp?rev=108099&r1=108098&r2=108099&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp (original)
> +++ llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp Sun Jul 11 14:19:13 2010
> @@ -174,61 +174,6 @@
> llvm_unreachable("Can't load this register from stack slot");
> }
>
> -MachineInstr *SparcInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
> - MachineInstr* MI,
> - const SmallVectorImpl<unsigned> &Ops,
> - int FI) const {
> - if (Ops.size() != 1) return NULL;
> -
> - unsigned OpNum = Ops[0];
> - bool isFloat = false;
> - MachineInstr *NewMI = NULL;
> - switch (MI->getOpcode()) {
> - case SP::ORrr:
> - if (MI->getOperand(1).isReg() && MI->getOperand(1).getReg() == SP::G0&&
> - MI->getOperand(0).isReg() && MI->getOperand(2).isReg()) {
> - if (OpNum == 0) // COPY -> STORE
> - NewMI = BuildMI(MF, MI->getDebugLoc(), get(SP::STri))
> - .addFrameIndex(FI)
> - .addImm(0)
> - .addReg(MI->getOperand(2).getReg());
> - else // COPY -> LOAD
> - NewMI = BuildMI(MF, MI->getDebugLoc(), get(SP::LDri),
> - MI->getOperand(0).getReg())
> - .addFrameIndex(FI)
> - .addImm(0);
> - }
> - break;
> - case SP::FMOVS:
> - isFloat = true;
> - // FALLTHROUGH
> - case SP::FMOVD:
> - if (OpNum == 0) { // COPY -> STORE
> - unsigned SrcReg = MI->getOperand(1).getReg();
> - bool isKill = MI->getOperand(1).isKill();
> - bool isUndef = MI->getOperand(1).isUndef();
> - NewMI = BuildMI(MF, MI->getDebugLoc(),
> - get(isFloat ? SP::STFri : SP::STDFri))
> - .addFrameIndex(FI)
> - .addImm(0)
> - .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef));
> - } else { // COPY -> LOAD
> - unsigned DstReg = MI->getOperand(0).getReg();
> - bool isDead = MI->getOperand(0).isDead();
> - bool isUndef = MI->getOperand(0).isUndef();
> - NewMI = BuildMI(MF, MI->getDebugLoc(),
> - get(isFloat ? SP::LDFri : SP::LDDFri))
> - .addReg(DstReg, RegState::Define |
> - getDeadRegState(isDead) | getUndefRegState(isUndef))
> - .addFrameIndex(FI)
> - .addImm(0);
> - }
> - break;
> - }
> -
> - return NewMI;
> -}
> -
> unsigned SparcInstrInfo::getGlobalBaseReg(MachineFunction *MF) const
> {
> SparcMachineFunctionInfo *SparcFI = MF->getInfo<SparcMachineFunctionInfo>();
>
> Modified: llvm/trunk/lib/Target/Sparc/SparcInstrInfo.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcInstrInfo.h?rev=108099&r1=108098&r2=108099&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Sparc/SparcInstrInfo.h (original)
> +++ llvm/trunk/lib/Target/Sparc/SparcInstrInfo.h Sun Jul 11 14:19:13 2010
> @@ -88,18 +88,6 @@
> const TargetRegisterClass *RC,
> const TargetRegisterInfo *TRI) const;
>
> - virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
> - MachineInstr* MI,
> - const SmallVectorImpl<unsigned> &Ops,
> - int FrameIndex) const;
> -
> - virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
> - MachineInstr* MI,
> - const SmallVectorImpl<unsigned> &Ops,
> - MachineInstr* LoadMI) const {
> - return 0;
> - }
> -
> unsigned getGlobalBaseReg(MachineFunction *MF) const;
> };
>
>
>
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