[llvm-commits] [llvm] r107943 - in /llvm/trunk: include/llvm/CodeGen/ include/llvm/Support/ include/llvm/Target/ lib/CodeGen/ lib/CodeGen/SelectionDAG/ lib/Target/X86/ lib/Target/XCore/ test/CodeGen/X86/
Bob Wilson
bob.wilson at apple.com
Fri Jul 9 09:40:34 PDT 2010
Dan, I've reverted this. It was badly broken for i386. Apple's driver-driver segfaulted very early, and Jean-Daniel Dupas posted a testcase demonstrating a problem on llvm-dev.
On Jul 8, 2010, at 5:39 PM, Dan Gohman wrote:
> Author: djg
> Date: Thu Jul 8 19:39:23 2010
> New Revision: 107943
>
> URL: http://llvm.org/viewvc/llvm-project?rev=107943&view=rev
> Log:
> Re-apply bottom-up fast-isel, with fixes. Be very careful to avoid emitting
> a DBG_VALUE after a terminator, or emitting any instructions before an EH_LABEL.
>
> Modified:
> llvm/trunk/include/llvm/CodeGen/CallingConvLower.h
> llvm/trunk/include/llvm/CodeGen/FastISel.h
> llvm/trunk/include/llvm/CodeGen/FunctionLoweringInfo.h
> llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h
> llvm/trunk/include/llvm/Support/PassNameParser.h
> llvm/trunk/include/llvm/Target/TargetLowering.h
> llvm/trunk/lib/CodeGen/CallingConvLower.cpp
> llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp
> llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
> llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
> llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
> llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
> llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
> llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
> llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
> llvm/trunk/lib/Target/X86/X86FastISel.cpp
> llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
> llvm/trunk/lib/Target/X86/X86ISelLowering.h
> llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp
> llvm/trunk/lib/Target/XCore/XCoreISelLowering.h
> llvm/trunk/test/CodeGen/X86/fast-isel-loads.ll
> llvm/trunk/test/CodeGen/X86/fast-isel.ll
>
> Modified: llvm/trunk/include/llvm/CodeGen/CallingConvLower.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/CallingConvLower.h?rev=107943&r1=107942&r2=107943&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/CodeGen/CallingConvLower.h (original)
> +++ llvm/trunk/include/llvm/CodeGen/CallingConvLower.h Thu Jul 8 19:39:23 2010
> @@ -188,8 +188,7 @@
> /// CheckReturn - Analyze the return values of a function, returning
> /// true if the return can be performed without sret-demotion, and
> /// false otherwise.
> - bool CheckReturn(const SmallVectorImpl<EVT> &OutTys,
> - const SmallVectorImpl<ISD::ArgFlagsTy> &ArgsFlags,
> + bool CheckReturn(const SmallVectorImpl<ISD::OutputArg> &ArgsFlags,
> CCAssignFn Fn);
>
> /// AnalyzeCallOperands - Analyze the outgoing arguments to a call,
>
> Modified: llvm/trunk/include/llvm/CodeGen/FastISel.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/FastISel.h?rev=107943&r1=107942&r2=107943&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/CodeGen/FastISel.h (original)
> +++ llvm/trunk/include/llvm/CodeGen/FastISel.h Thu Jul 8 19:39:23 2010
> @@ -19,6 +19,7 @@
> #include "llvm/ADT/SmallSet.h"
> #endif
> #include "llvm/CodeGen/ValueTypes.h"
> +#include "llvm/CodeGen/MachineBasicBlock.h"
>
> namespace llvm {
>
> @@ -44,7 +45,6 @@
> /// lowering, but runs quickly.
> class FastISel {
> protected:
> - MachineBasicBlock *MBB;
> DenseMap<const Value *, unsigned> LocalValueMap;
> FunctionLoweringInfo &FuncInfo;
> MachineRegisterInfo &MRI;
> @@ -56,23 +56,21 @@
> const TargetInstrInfo &TII;
> const TargetLowering &TLI;
> const TargetRegisterInfo &TRI;
> - bool IsBottomUp;
> + MachineInstr *LastLocalValue;
>
> public:
> + /// getLastLocalValue - Return the position of the last instruction
> + /// emitted for materializing constants for use in the current block.
> + MachineInstr *getLastLocalValue() { return LastLocalValue; }
> +
> + /// setLastLocalValue - Update the position of the last instruction
> + /// emitted for materializing constants for use in the current block.
> + void setLastLocalValue(MachineInstr *I) { LastLocalValue = I; }
> +
> /// startNewBlock - Set the current block to which generated machine
> /// instructions will be appended, and clear the local CSE map.
> ///
> - void startNewBlock(MachineBasicBlock *mbb) {
> - setCurrentBlock(mbb);
> - LocalValueMap.clear();
> - }
> -
> - /// setCurrentBlock - Set the current block to which generated machine
> - /// instructions will be appended.
> - ///
> - void setCurrentBlock(MachineBasicBlock *mbb) {
> - MBB = mbb;
> - }
> + void startNewBlock();
>
> /// getCurDebugLoc() - Return current debug location information.
> DebugLoc getCurDebugLoc() const { return DL; }
> @@ -104,6 +102,17 @@
> /// index value.
> std::pair<unsigned, bool> getRegForGEPIndex(const Value *V);
>
> + /// recomputeInsertPt - Reset InsertPt to prepare for insterting instructions
> + /// into the current block.
> + void recomputeInsertPt();
> +
> + /// enterLocalValueArea - Prepare InsertPt to begin inserting instructions
> + /// into the local value area and return the old insert position.
> + MachineBasicBlock::iterator enterLocalValueArea();
> +
> + /// leaveLocalValueArea - Reset InsertPt to the given old insert position
> + void leaveLocalValueArea(MachineBasicBlock::iterator OldInsertPt);
> +
> virtual ~FastISel();
>
> protected:
>
> Modified: llvm/trunk/include/llvm/CodeGen/FunctionLoweringInfo.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/FunctionLoweringInfo.h?rev=107943&r1=107942&r2=107943&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/CodeGen/FunctionLoweringInfo.h (original)
> +++ llvm/trunk/include/llvm/CodeGen/FunctionLoweringInfo.h Thu Jul 8 19:39:23 2010
> @@ -25,6 +25,7 @@
> #endif
> #include "llvm/CodeGen/ValueTypes.h"
> #include "llvm/CodeGen/ISDOpcodes.h"
> +#include "llvm/CodeGen/MachineBasicBlock.h"
> #include "llvm/Support/CallSite.h"
> #include <vector>
>
> @@ -80,6 +81,15 @@
> /// function arguments that are inserted after scheduling is completed.
> SmallVector<MachineInstr*, 8> ArgDbgValues;
>
> + /// RegFixups - Registers which need to be replaced after isel is done.
> + DenseMap<unsigned, unsigned> RegFixups;
> +
> + /// MBB - The current block.
> + MachineBasicBlock *MBB;
> +
> + /// MBB - The current insert position inside the current block.
> + MachineBasicBlock::iterator InsertPt;
> +
> #ifndef NDEBUG
> SmallSet<const Instruction *, 8> CatchInfoLost;
> SmallSet<const Instruction *, 8> CatchInfoFound;
>
> Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h?rev=107943&r1=107942&r2=107943&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h (original)
> +++ llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h Thu Jul 8 19:39:23 2010
> @@ -280,15 +280,14 @@
> SDNode *MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTs,
> const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo);
>
> - void PrepareEHLandingPad(MachineBasicBlock *BB);
> + void PrepareEHLandingPad();
> void SelectAllBasicBlocks(const Function &Fn);
> - void FinishBasicBlock(MachineBasicBlock *BB);
> + void FinishBasicBlock();
>
> - MachineBasicBlock *SelectBasicBlock(MachineBasicBlock *BB,
> - BasicBlock::const_iterator Begin,
> - BasicBlock::const_iterator End,
> - bool &HadTailCall);
> - MachineBasicBlock *CodeGenAndEmitDAG(MachineBasicBlock *BB);
> + void SelectBasicBlock(BasicBlock::const_iterator Begin,
> + BasicBlock::const_iterator End,
> + bool &HadTailCall);
> + void CodeGenAndEmitDAG();
> void LowerArguments(const BasicBlock *BB);
>
> void ComputeLiveOutVRegInfo();
>
> Modified: llvm/trunk/include/llvm/Support/PassNameParser.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/PassNameParser.h?rev=107943&r1=107942&r2=107943&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/Support/PassNameParser.h (original)
> +++ llvm/trunk/include/llvm/Support/PassNameParser.h Thu Jul 8 19:39:23 2010
> @@ -69,6 +69,7 @@
> virtual void passRegistered(const PassInfo *P) {
> if (ignorablePass(P) || !Opt) return;
> if (findOption(P->getPassArgument()) != getNumOptions()) {
> + return;
> errs() << "Two passes with the same argument (-"
> << P->getPassArgument() << ") attempted to be registered!\n";
> llvm_unreachable(0);
>
> Modified: llvm/trunk/include/llvm/Target/TargetLowering.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetLowering.h?rev=107943&r1=107942&r2=107943&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/Target/TargetLowering.h (original)
> +++ llvm/trunk/include/llvm/Target/TargetLowering.h Thu Jul 8 19:39:23 2010
> @@ -24,6 +24,7 @@
>
> #include "llvm/CallingConv.h"
> #include "llvm/InlineAsm.h"
> +#include "llvm/Attributes.h"
> #include "llvm/CodeGen/SelectionDAGNodes.h"
> #include "llvm/CodeGen/RuntimeLibcalls.h"
> #include "llvm/ADT/APFloat.h"
> @@ -1159,8 +1160,7 @@
> /// registers. If false is returned, an sret-demotion is performed.
> ///
> virtual bool CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
> - const SmallVectorImpl<EVT> &OutTys,
> - const SmallVectorImpl<ISD::ArgFlagsTy> &ArgsFlags,
> + const SmallVectorImpl<ISD::OutputArg> &Outs,
> LLVMContext &Context) const
> {
> // Return true by default to get preexisting behavior.
> @@ -1656,6 +1656,15 @@
> /// optimization.
> bool benefitFromCodePlacementOpt;
> };
> +
> +/// GetReturnInfo - Given an LLVM IR type and return type attributes,
> +/// compute the return value EVTs and flags, and optionally also
> +/// the offsets, if the return value is being lowered to memory.
> +void GetReturnInfo(const Type* ReturnType, Attributes attr,
> + SmallVectorImpl<ISD::OutputArg> &Outs,
> + const TargetLowering &TLI,
> + SmallVectorImpl<uint64_t> *Offsets = 0);
> +
> } // end llvm namespace
>
> #endif
>
> Modified: llvm/trunk/lib/CodeGen/CallingConvLower.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/CallingConvLower.cpp?rev=107943&r1=107942&r2=107943&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/CallingConvLower.cpp (original)
> +++ llvm/trunk/lib/CodeGen/CallingConvLower.cpp Thu Jul 8 19:39:23 2010
> @@ -80,13 +80,12 @@
>
> /// CheckReturn - Analyze the return values of a function, returning true if
> /// the return can be performed without sret-demotion, and false otherwise.
> -bool CCState::CheckReturn(const SmallVectorImpl<EVT> &OutTys,
> - const SmallVectorImpl<ISD::ArgFlagsTy> &ArgsFlags,
> +bool CCState::CheckReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
> CCAssignFn Fn) {
> // Determine which register each value should be copied into.
> - for (unsigned i = 0, e = OutTys.size(); i != e; ++i) {
> - EVT VT = OutTys[i];
> - ISD::ArgFlagsTy ArgFlags = ArgsFlags[i];
> + for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
> + EVT VT = Outs[i].VT;
> + ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
> if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this))
> return false;
> }
>
> Modified: llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp?rev=107943&r1=107942&r2=107943&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp (original)
> +++ llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp Thu Jul 8 19:39:23 2010
> @@ -329,19 +329,15 @@
> if (OptLevel != CodeGenOpt::None)
> PM.add(createOptimizePHIsPass());
>
> - // Delete dead machine instructions regardless of optimization level.
> - //
> - // At -O0, fast-isel frequently creates dead instructions.
> - //
> - // With optimization, dead code should already be eliminated. However
> - // there is one known exception: lowered code for arguments that are only
> - // used by tail calls, where the tail calls reuse the incoming stack
> - // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
> - PM.add(createDeadMachineInstructionElimPass());
> - printAndVerify(PM, "After codegen DCE pass",
> - /* allowDoubleDefs= */ true);
> -
> if (OptLevel != CodeGenOpt::None) {
> + // With optimization, dead code should already be eliminated. However
> + // there is one known exception: lowered code for arguments that are only
> + // used by tail calls, where the tail calls reuse the incoming stack
> + // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
> + PM.add(createDeadMachineInstructionElimPass());
> + printAndVerify(PM, "After codegen DCE pass",
> + /* allowDoubleDefs= */ true);
> +
> PM.add(createOptimizeExtsPass());
> if (!DisableMachineLICM)
> PM.add(createMachineLICMPass());
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=107943&r1=107942&r2=107943&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Thu Jul 8 19:39:23 2010
> @@ -57,6 +57,25 @@
> #include "llvm/Support/ErrorHandling.h"
> using namespace llvm;
>
> +/// startNewBlock - Set the current block to which generated machine
> +/// instructions will be appended, and clear the local CSE map.
> +///
> +void FastISel::startNewBlock() {
> + LocalValueMap.clear();
> +
> + // Start out as null, meaining no local-value instructions have
> + // been emitted.
> + LastLocalValue = 0;
> +
> + // Advance the last local value past any EH_LABEL instructions.
> + MachineBasicBlock::iterator
> + I = FuncInfo.MBB->begin(), E = FuncInfo.MBB->end();
> + while (I != E && I->getOpcode() == TargetOpcode::EH_LABEL) {
> + LastLocalValue = I;
> + ++I;
> + }
> +}
> +
> bool FastISel::hasTrivialKill(const Value *V) const {
> // Don't consider constants or arguments to have trivial kills.
> const Instruction *I = dyn_cast<Instruction>(V);
> @@ -101,24 +120,30 @@
> // only locally. This is because Instructions already have the SSA
> // def-dominates-use requirement enforced.
> DenseMap<const Value *, unsigned>::iterator I = FuncInfo.ValueMap.find(V);
> - if (I != FuncInfo.ValueMap.end())
> - return I->second;
> + if (I != FuncInfo.ValueMap.end()) {
> + unsigned Reg = I->second;
> + return Reg;
> + }
> unsigned Reg = LocalValueMap[V];
> if (Reg != 0)
> return Reg;
>
> // In bottom-up mode, just create the virtual register which will be used
> // to hold the value. It will be materialized later.
> - if (IsBottomUp) {
> - Reg = createResultReg(TLI.getRegClassFor(VT));
> - if (isa<Instruction>(V))
> - FuncInfo.ValueMap[V] = Reg;
> - else
> - LocalValueMap[V] = Reg;
> - return Reg;
> - }
> + if (isa<Instruction>(V) &&
> + (!isa<AllocaInst>(V) ||
> + !FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(V))))
> + return FuncInfo.InitializeRegForValue(V);
> +
> + MachineBasicBlock::iterator SaveInsertPt = enterLocalValueArea();
> +
> + // Materialize the value in a register. Emit any instructions in the
> + // local value area.
> + Reg = materializeRegForValue(V, VT);
> +
> + leaveLocalValueArea(SaveInsertPt);
>
> - return materializeRegForValue(V, VT);
> + return Reg;
> }
>
> /// materializeRegForValue - Helper for getRegForVale. This function is
> @@ -169,7 +194,8 @@
> Reg = lookUpRegForValue(Op);
> } else if (isa<UndefValue>(V)) {
> Reg = createResultReg(TLI.getRegClassFor(VT));
> - BuildMI(MBB, DL, TII.get(TargetOpcode::IMPLICIT_DEF), Reg);
> + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
> + TII.get(TargetOpcode::IMPLICIT_DEF), Reg);
> }
>
> // If target-independent code couldn't handle the value, give target-specific
> @@ -179,8 +205,10 @@
>
> // Don't cache constant materializations in the general ValueMap.
> // To do so would require tracking what uses they dominate.
> - if (Reg != 0)
> + if (Reg != 0) {
> LocalValueMap[V] = Reg;
> + LastLocalValue = MRI.getVRegDef(Reg);
> + }
> return Reg;
> }
>
> @@ -209,12 +237,15 @@
>
> unsigned &AssignedReg = FuncInfo.ValueMap[I];
> if (AssignedReg == 0)
> + // Use the new register.
> AssignedReg = Reg;
> else if (Reg != AssignedReg) {
> - const TargetRegisterClass *RegClass = MRI.getRegClass(Reg);
> - TII.copyRegToReg(*MBB, MBB->end(), AssignedReg,
> - Reg, RegClass, RegClass, DL);
> + // Arrange for uses of AssignedReg to be replaced by uses of Reg.
> + FuncInfo.RegFixups[AssignedReg] = Reg;
> +
> + AssignedReg = Reg;
> }
> +
> return AssignedReg;
> }
>
> @@ -242,6 +273,33 @@
> return std::pair<unsigned, bool>(IdxN, IdxNIsKill);
> }
>
> +void FastISel::recomputeInsertPt() {
> + if (getLastLocalValue()) {
> + FuncInfo.InsertPt = getLastLocalValue();
> + ++FuncInfo.InsertPt;
> + } else
> + FuncInfo.InsertPt = FuncInfo.MBB->getFirstNonPHI();
> +
> + // Now skip past any EH_LABELs, which must remain at the beginning.
> + while (FuncInfo.InsertPt != FuncInfo.MBB->end() &&
> + FuncInfo.InsertPt->getOpcode() == TargetOpcode::EH_LABEL)
> + ++FuncInfo.InsertPt;
> +}
> +
> +MachineBasicBlock::iterator FastISel::enterLocalValueArea() {
> + MachineBasicBlock::iterator OldInsertPt = FuncInfo.InsertPt;
> + recomputeInsertPt();
> + return OldInsertPt;
> +}
> +
> +void FastISel::leaveLocalValueArea(MachineBasicBlock::iterator OldInsertPt) {
> + if (FuncInfo.InsertPt != FuncInfo.MBB->begin())
> + LastLocalValue = llvm::prior(FuncInfo.InsertPt);
> +
> + // Restore the previous insert position.
> + FuncInfo.InsertPt = OldInsertPt;
> +}
> +
> /// SelectBinaryOp - Select and emit code for a binary operator instruction,
> /// which has an opcode which directly corresponds to the given ISD opcode.
> ///
> @@ -434,23 +492,28 @@
> if (!V) {
> // Currently the optimizer can produce this; insert an undef to
> // help debugging. Probably the optimizer should not do this.
> - BuildMI(MBB, DL, II).addReg(0U).addImm(DI->getOffset()).
> - addMetadata(DI->getVariable());
> + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
> + .addReg(0U).addImm(DI->getOffset())
> + .addMetadata(DI->getVariable());
> } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
> - BuildMI(MBB, DL, II).addImm(CI->getZExtValue()).addImm(DI->getOffset()).
> - addMetadata(DI->getVariable());
> + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
> + .addImm(CI->getZExtValue()).addImm(DI->getOffset())
> + .addMetadata(DI->getVariable());
> } else if (const ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
> - BuildMI(MBB, DL, II).addFPImm(CF).addImm(DI->getOffset()).
> - addMetadata(DI->getVariable());
> + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
> + .addFPImm(CF).addImm(DI->getOffset())
> + .addMetadata(DI->getVariable());
> } else if (unsigned Reg = lookUpRegForValue(V)) {
> - BuildMI(MBB, DL, II).addReg(Reg, RegState::Debug).addImm(DI->getOffset()).
> - addMetadata(DI->getVariable());
> + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
> + .addReg(Reg, RegState::Debug).addImm(DI->getOffset())
> + .addMetadata(DI->getVariable());
> } else {
> // We can't yet handle anything else here because it would require
> // generating code, thus altering codegen because of debug info.
> // Insert an undef so we can see what we dropped.
> - BuildMI(MBB, DL, II).addReg(0U).addImm(DI->getOffset()).
> - addMetadata(DI->getVariable());
> + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
> + .addReg(0U).addImm(DI->getOffset())
> + .addMetadata(DI->getVariable());
> }
> return true;
> }
> @@ -459,12 +522,13 @@
> switch (TLI.getOperationAction(ISD::EXCEPTIONADDR, VT)) {
> default: break;
> case TargetLowering::Expand: {
> - assert(MBB->isLandingPad() && "Call to eh.exception not in landing pad!");
> + assert(FuncInfo.MBB->isLandingPad() &&
> + "Call to eh.exception not in landing pad!");
> unsigned Reg = TLI.getExceptionAddressRegister();
> const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
> unsigned ResultReg = createResultReg(RC);
> - bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
> - Reg, RC, RC, DL);
> + bool InsertedCopy = TII.copyRegToReg(*FuncInfo.MBB, FuncInfo.InsertPt,
> + ResultReg, Reg, RC, RC, DL);
> assert(InsertedCopy && "Can't copy address registers!");
> InsertedCopy = InsertedCopy;
> UpdateValueMap(I, ResultReg);
> @@ -478,23 +542,23 @@
> switch (TLI.getOperationAction(ISD::EHSELECTION, VT)) {
> default: break;
> case TargetLowering::Expand: {
> - if (MBB->isLandingPad())
> - AddCatchInfo(*cast<CallInst>(I), &FuncInfo.MF->getMMI(), MBB);
> + if (FuncInfo.MBB->isLandingPad())
> + AddCatchInfo(*cast<CallInst>(I), &FuncInfo.MF->getMMI(), FuncInfo.MBB);
> else {
> #ifndef NDEBUG
> FuncInfo.CatchInfoLost.insert(cast<CallInst>(I));
> #endif
> // FIXME: Mark exception selector register as live in. Hack for PR1508.
> unsigned Reg = TLI.getExceptionSelectorRegister();
> - if (Reg) MBB->addLiveIn(Reg);
> + if (Reg) FuncInfo.MBB->addLiveIn(Reg);
> }
>
> unsigned Reg = TLI.getExceptionSelectorRegister();
> EVT SrcVT = TLI.getPointerTy();
> const TargetRegisterClass *RC = TLI.getRegClassFor(SrcVT);
> unsigned ResultReg = createResultReg(RC);
> - bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, Reg,
> - RC, RC, DL);
> + bool InsertedCopy = TII.copyRegToReg(*FuncInfo.MBB, FuncInfo.InsertPt,
> + ResultReg, Reg, RC, RC, DL);
> assert(InsertedCopy && "Can't copy address registers!");
> InsertedCopy = InsertedCopy;
>
> @@ -613,8 +677,9 @@
> TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT);
> ResultReg = createResultReg(DstClass);
>
> - bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
> - Op0, DstClass, SrcClass, DL);
> + bool InsertedCopy = TII.copyRegToReg(*FuncInfo.MBB, FuncInfo.InsertPt,
> + ResultReg, Op0,
> + DstClass, SrcClass, DL);
> if (!InsertedCopy)
> ResultReg = 0;
> }
> @@ -662,13 +727,14 @@
> /// the CFG.
> void
> FastISel::FastEmitBranch(MachineBasicBlock *MSucc, DebugLoc DL) {
> - if (MBB->isLayoutSuccessor(MSucc)) {
> + if (FuncInfo.MBB->isLayoutSuccessor(MSucc)) {
> // The unconditional fall-through case, which needs no instructions.
> } else {
> // The unconditional branch case.
> - TII.InsertBranch(*MBB, MSucc, NULL, SmallVector<MachineOperand, 0>(), DL);
> + TII.InsertBranch(*FuncInfo.MBB, MSucc, NULL,
> + SmallVector<MachineOperand, 0>(), DL);
> }
> - MBB->addSuccessor(MSucc);
> + FuncInfo.MBB->addSuccessor(MSucc);
> }
>
> /// SelectFNeg - Emit an FNeg operation.
> @@ -727,11 +793,19 @@
> BasicBlock::iterator ScanFrom = LI;
> if (const Value *V = FindAvailableLoadedValue(LI->getPointerOperand(),
> LI->getParent(), ScanFrom)) {
> + if (!V->use_empty() &&
> + (!isa<Instruction>(V) ||
> + cast<Instruction>(V)->getParent() == LI->getParent() ||
> + (isa<AllocaInst>(V) &&
> + FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(V)))) &&
> + (!isa<Argument>(V) ||
> + LI->getParent() == &LI->getParent()->getParent()->getEntryBlock())) {
> unsigned ResultReg = getRegForValue(V);
> if (ResultReg != 0) {
> UpdateValueMap(I, ResultReg);
> return true;
> }
> + }
> }
> }
>
> @@ -854,8 +928,7 @@
> }
>
> FastISel::FastISel(FunctionLoweringInfo &funcInfo)
> - : MBB(0),
> - FuncInfo(funcInfo),
> + : FuncInfo(funcInfo),
> MRI(FuncInfo.MF->getRegInfo()),
> MFI(*FuncInfo.MF->getFrameInfo()),
> MCP(*FuncInfo.MF->getConstantPool()),
> @@ -863,8 +936,7 @@
> TD(*TM.getTargetData()),
> TII(*TM.getInstrInfo()),
> TLI(*TM.getTargetLowering()),
> - TRI(*TM.getRegisterInfo()),
> - IsBottomUp(false) {
> + TRI(*TM.getRegisterInfo()) {
> }
>
> FastISel::~FastISel() {}
> @@ -993,7 +1065,7 @@
> unsigned ResultReg = createResultReg(RC);
> const TargetInstrDesc &II = TII.get(MachineInstOpcode);
>
> - BuildMI(MBB, DL, II, ResultReg);
> + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg);
> return ResultReg;
> }
>
> @@ -1004,11 +1076,14 @@
> const TargetInstrDesc &II = TII.get(MachineInstOpcode);
>
> if (II.getNumDefs() >= 1)
> - BuildMI(MBB, DL, II, ResultReg).addReg(Op0, Op0IsKill * RegState::Kill);
> + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
> + .addReg(Op0, Op0IsKill * RegState::Kill);
> else {
> - BuildMI(MBB, DL, II).addReg(Op0, Op0IsKill * RegState::Kill);
> - bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
> - II.ImplicitDefs[0], RC, RC, DL);
> + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
> + .addReg(Op0, Op0IsKill * RegState::Kill);
> + bool InsertedCopy = TII.copyRegToReg(*FuncInfo.MBB, FuncInfo.InsertPt,
> + ResultReg, II.ImplicitDefs[0],
> + RC, RC, DL);
> if (!InsertedCopy)
> ResultReg = 0;
> }
> @@ -1024,15 +1099,16 @@
> const TargetInstrDesc &II = TII.get(MachineInstOpcode);
>
> if (II.getNumDefs() >= 1)
> - BuildMI(MBB, DL, II, ResultReg)
> + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
> .addReg(Op0, Op0IsKill * RegState::Kill)
> .addReg(Op1, Op1IsKill * RegState::Kill);
> else {
> - BuildMI(MBB, DL, II)
> + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
> .addReg(Op0, Op0IsKill * RegState::Kill)
> .addReg(Op1, Op1IsKill * RegState::Kill);
> - bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
> - II.ImplicitDefs[0], RC, RC, DL);
> + bool InsertedCopy = TII.copyRegToReg(*FuncInfo.MBB, FuncInfo.InsertPt,
> + ResultReg, II.ImplicitDefs[0],
> + RC, RC, DL);
> if (!InsertedCopy)
> ResultReg = 0;
> }
> @@ -1047,15 +1123,16 @@
> const TargetInstrDesc &II = TII.get(MachineInstOpcode);
>
> if (II.getNumDefs() >= 1)
> - BuildMI(MBB, DL, II, ResultReg)
> + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
> .addReg(Op0, Op0IsKill * RegState::Kill)
> .addImm(Imm);
> else {
> - BuildMI(MBB, DL, II)
> + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
> .addReg(Op0, Op0IsKill * RegState::Kill)
> .addImm(Imm);
> - bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
> - II.ImplicitDefs[0], RC, RC, DL);
> + bool InsertedCopy = TII.copyRegToReg(*FuncInfo.MBB, FuncInfo.InsertPt,
> + ResultReg, II.ImplicitDefs[0],
> + RC, RC, DL);
> if (!InsertedCopy)
> ResultReg = 0;
> }
> @@ -1070,15 +1147,16 @@
> const TargetInstrDesc &II = TII.get(MachineInstOpcode);
>
> if (II.getNumDefs() >= 1)
> - BuildMI(MBB, DL, II, ResultReg)
> + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
> .addReg(Op0, Op0IsKill * RegState::Kill)
> .addFPImm(FPImm);
> else {
> - BuildMI(MBB, DL, II)
> + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
> .addReg(Op0, Op0IsKill * RegState::Kill)
> .addFPImm(FPImm);
> - bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
> - II.ImplicitDefs[0], RC, RC, DL);
> + bool InsertedCopy = TII.copyRegToReg(*FuncInfo.MBB, FuncInfo.InsertPt,
> + ResultReg, II.ImplicitDefs[0],
> + RC, RC, DL);
> if (!InsertedCopy)
> ResultReg = 0;
> }
> @@ -1094,17 +1172,18 @@
> const TargetInstrDesc &II = TII.get(MachineInstOpcode);
>
> if (II.getNumDefs() >= 1)
> - BuildMI(MBB, DL, II, ResultReg)
> + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
> .addReg(Op0, Op0IsKill * RegState::Kill)
> .addReg(Op1, Op1IsKill * RegState::Kill)
> .addImm(Imm);
> else {
> - BuildMI(MBB, DL, II)
> + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
> .addReg(Op0, Op0IsKill * RegState::Kill)
> .addReg(Op1, Op1IsKill * RegState::Kill)
> .addImm(Imm);
> - bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
> - II.ImplicitDefs[0], RC, RC, DL);
> + bool InsertedCopy = TII.copyRegToReg(*FuncInfo.MBB, FuncInfo.InsertPt,
> + ResultReg, II.ImplicitDefs[0],
> + RC, RC, DL);
> if (!InsertedCopy)
> ResultReg = 0;
> }
> @@ -1118,11 +1197,12 @@
> const TargetInstrDesc &II = TII.get(MachineInstOpcode);
>
> if (II.getNumDefs() >= 1)
> - BuildMI(MBB, DL, II, ResultReg).addImm(Imm);
> + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg).addImm(Imm);
> else {
> - BuildMI(MBB, DL, II).addImm(Imm);
> - bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
> - II.ImplicitDefs[0], RC, RC, DL);
> + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II).addImm(Imm);
> + bool InsertedCopy = TII.copyRegToReg(*FuncInfo.MBB, FuncInfo.InsertPt,
> + ResultReg, II.ImplicitDefs[0],
> + RC, RC, DL);
> if (!InsertedCopy)
> ResultReg = 0;
> }
> @@ -1135,7 +1215,8 @@
> unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
> assert(TargetRegisterInfo::isVirtualRegister(Op0) &&
> "Cannot yet extract from physregs");
> - BuildMI(MBB, DL, TII.get(TargetOpcode::COPY), ResultReg)
> + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
> + DL, TII.get(TargetOpcode::COPY), ResultReg)
> .addReg(Op0, getKillRegState(Op0IsKill), Idx);
> return ResultReg;
> }
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp?rev=107943&r1=107942&r2=107943&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp Thu Jul 8 19:39:23 2010
> @@ -78,6 +78,13 @@
> MF = &mf;
> RegInfo = &MF->getRegInfo();
>
> + // Check whether the function can return without sret-demotion.
> + SmallVector<ISD::OutputArg, 4> Outs;
> + GetReturnInfo(Fn->getReturnType(),
> + Fn->getAttributes().getRetAttributes(), Outs, TLI);
> + CanLowerReturn = TLI.CanLowerReturn(Fn->getCallingConv(), Fn->isVarArg(),
> + Outs, Fn->getContext());
> +
> // Create a vreg for each argument register that is not dead and is used
> // outside of the entry block for the function.
> for (Function::const_arg_iterator AI = Fn->arg_begin(), E = Fn->arg_end();
> @@ -170,6 +177,7 @@
> #endif
> LiveOutRegInfo.clear();
> ArgDbgValues.clear();
> + RegFixups.clear();
> }
>
> /// CreateReg - Allocate a single virtual register for the given type.
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp?rev=107943&r1=107942&r2=107943&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp Thu Jul 8 19:39:23 2010
> @@ -734,8 +734,13 @@
> if (II.usesCustomInsertionHook()) {
> // Insert this instruction into the basic block using a target
> // specific inserter which may returns a new basic block.
> - MBB = TLI->EmitInstrWithCustomInserter(MI, MBB);
> - InsertPos = MBB->end();
> + bool AtEnd = InsertPos == MBB->end();
> + MachineBasicBlock *NewMBB = TLI->EmitInstrWithCustomInserter(MI, MBB);
> + if (NewMBB != MBB) {
> + if (AtEnd)
> + InsertPos = NewMBB->end();
> + MBB = NewMBB;
> + }
> return;
> }
>
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp?rev=107943&r1=107942&r2=107943&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp Thu Jul 8 19:39:23 2010
> @@ -519,13 +519,13 @@
> return;
>
> MachineBasicBlock *BB = Emitter.getBlock();
> - if (BB->empty() || BB->back().isPHI()) {
> + if (Emitter.getInsertPos() == BB->begin() || BB->back().isPHI()) {
> // Did not insert any instruction.
> Orders.push_back(std::make_pair(Order, (MachineInstr*)0));
> return;
> }
>
> - Orders.push_back(std::make_pair(Order, &BB->back()));
> + Orders.push_back(std::make_pair(Order, prior(Emitter.getInsertPos())));
> if (!N->getHasDebugValue())
> return;
> // Opportunistically insert immediate dbg_value uses, i.e. those with source
> @@ -564,7 +564,7 @@
> for (; PDI != PDE; ++PDI) {
> MachineInstr *DbgMI= Emitter.EmitDbgValue(*PDI, VRBaseMap);
> if (DbgMI)
> - BB->push_back(DbgMI);
> + BB->insert(InsertPos, DbgMI);
> }
> }
>
> @@ -608,9 +608,7 @@
> // Insert all the dbg_values which have not already been inserted in source
> // order sequence.
> if (HasDbg) {
> - MachineBasicBlock::iterator BBBegin = BB->empty() ? BB->end() : BB->begin();
> - while (BBBegin != BB->end() && BBBegin->isPHI())
> - ++BBBegin;
> + MachineBasicBlock::iterator BBBegin = BB->getFirstNonPHI();
>
> // Sort the source order instructions and use the order to insert debug
> // values.
> @@ -626,7 +624,6 @@
> // Insert all SDDbgValue's whose order(s) are before "Order".
> if (!MI)
> continue;
> - MachineBasicBlock *MIBB = MI->getParent();
> #ifndef NDEBUG
> unsigned LastDIOrder = 0;
> #endif
> @@ -646,7 +643,7 @@
> BB->insert(BBBegin, DbgMI);
> else {
> MachineBasicBlock::iterator Pos = MI;
> - MIBB->insert(llvm::next(Pos), DbgMI);
> + BB->insert(llvm::next(Pos), DbgMI);
> }
> }
> }
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=107943&r1=107942&r2=107943&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Thu Jul 8 19:39:23 2010
> @@ -951,79 +951,16 @@
>
> // If this is an instruction which fast-isel has deferred, select it now.
> if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
> - assert(Inst->isSafeToSpeculativelyExecute() &&
> - "Instruction with side effects deferred!");
> - visit(*Inst);
> - DenseMap<const Value *, SDValue>::iterator NIt = NodeMap.find(Inst);
> - if (NIt != NodeMap.end() && NIt->second.getNode())
> - return NIt->second;
> + unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
> + RegsForValue RFV(*DAG.getContext(), TLI, InReg, Inst->getType());
> + SDValue Chain = DAG.getEntryNode();
> + return RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain, NULL);
> }
>
> llvm_unreachable("Can't get register for value!");
> return SDValue();
> }
>
> -/// Get the EVTs and ArgFlags collections that represent the legalized return
> -/// type of the given function. This does not require a DAG or a return value,
> -/// and is suitable for use before any DAGs for the function are constructed.
> -static void getReturnInfo(const Type* ReturnType,
> - Attributes attr, SmallVectorImpl<EVT> &OutVTs,
> - SmallVectorImpl<ISD::ArgFlagsTy> &OutFlags,
> - const TargetLowering &TLI,
> - SmallVectorImpl<uint64_t> *Offsets = 0) {
> - SmallVector<EVT, 4> ValueVTs;
> - ComputeValueVTs(TLI, ReturnType, ValueVTs);
> - unsigned NumValues = ValueVTs.size();
> - if (NumValues == 0) return;
> - unsigned Offset = 0;
> -
> - for (unsigned j = 0, f = NumValues; j != f; ++j) {
> - EVT VT = ValueVTs[j];
> - ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
> -
> - if (attr & Attribute::SExt)
> - ExtendKind = ISD::SIGN_EXTEND;
> - else if (attr & Attribute::ZExt)
> - ExtendKind = ISD::ZERO_EXTEND;
> -
> - // FIXME: C calling convention requires the return type to be promoted to
> - // at least 32-bit. But this is not necessary for non-C calling
> - // conventions. The frontend should mark functions whose return values
> - // require promoting with signext or zeroext attributes.
> - if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
> - EVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32);
> - if (VT.bitsLT(MinVT))
> - VT = MinVT;
> - }
> -
> - unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT);
> - EVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT);
> - unsigned PartSize = TLI.getTargetData()->getTypeAllocSize(
> - PartVT.getTypeForEVT(ReturnType->getContext()));
> -
> - // 'inreg' on function refers to return value
> - ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
> - if (attr & Attribute::InReg)
> - Flags.setInReg();
> -
> - // Propagate extension type if any
> - if (attr & Attribute::SExt)
> - Flags.setSExt();
> - else if (attr & Attribute::ZExt)
> - Flags.setZExt();
> -
> - for (unsigned i = 0; i < NumParts; ++i) {
> - OutVTs.push_back(PartVT);
> - OutFlags.push_back(Flags);
> - if (Offsets)
> - {
> - Offsets->push_back(Offset);
> - Offset += PartSize;
> - }
> - }
> - }
> -}
> -
> void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
> SDValue Chain = getControlRoot();
> SmallVector<ISD::OutputArg, 8> Outs;
> @@ -1320,7 +1257,7 @@
> }
>
> void SelectionDAGBuilder::visitBr(const BranchInst &I) {
> - MachineBasicBlock *BrMBB = FuncInfo.MBBMap[I.getParent()];
> + MachineBasicBlock *BrMBB = FuncInfo.MBB;
>
> // Update machine-CFG edges.
> MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
> @@ -1646,7 +1583,7 @@
> }
>
> void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
> - MachineBasicBlock *InvokeMBB = FuncInfo.MBBMap[I.getParent()];
> + MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
>
> // Retrieve successors.
> MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
> @@ -2174,7 +2111,7 @@
> }
>
> void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
> - MachineBasicBlock *SwitchMBB = FuncInfo.MBBMap[SI.getParent()];
> + MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
>
> // Figure out which block is immediately after the current one.
> MachineBasicBlock *NextBlock = 0;
> @@ -2240,7 +2177,7 @@
> }
>
> void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
> - MachineBasicBlock *IndirectBrMBB = FuncInfo.MBBMap[I.getParent()];
> + MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
>
> // Update machine-CFG edges with unique successors.
> SmallVector<BasicBlock*, 32> succs;
> @@ -3900,7 +3837,7 @@
> if (DV.isInlinedFnArgument(MF.getFunction()))
> return false;
>
> - MachineBasicBlock *MBB = FuncInfo.MBBMap[DI.getParent()];
> + MachineBasicBlock *MBB = FuncInfo.MBB;
> if (MBB != &MF.front())
> return false;
>
> @@ -4163,7 +4100,7 @@
> }
> case Intrinsic::eh_exception: {
> // Insert the EXCEPTIONADDR instruction.
> - assert(FuncInfo.MBBMap[I.getParent()]->isLandingPad() &&
> + assert(FuncInfo.MBB->isLandingPad() &&
> "Call to eh.exception not in landing pad!");
> SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
> SDValue Ops[1];
> @@ -4175,7 +4112,7 @@
> }
>
> case Intrinsic::eh_selector: {
> - MachineBasicBlock *CallMBB = FuncInfo.MBBMap[I.getParent()];
> + MachineBasicBlock *CallMBB = FuncInfo.MBB;
> MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
> if (CallMBB->isLandingPad())
> AddCatchInfo(I, &MMI, CallMBB);
> @@ -4185,7 +4122,7 @@
> #endif
> // FIXME: Mark exception selector register as live in. Hack for PR1508.
> unsigned Reg = TLI.getExceptionSelectorRegister();
> - if (Reg) FuncInfo.MBBMap[I.getParent()]->addLiveIn(Reg);
> + if (Reg) FuncInfo.MBB->addLiveIn(Reg);
> }
>
> // Insert the EHSELECTION instruction.
> @@ -4559,14 +4496,13 @@
> Args.reserve(CS.arg_size());
>
> // Check whether the function can return without sret-demotion.
> - SmallVector<EVT, 4> OutVTs;
> - SmallVector<ISD::ArgFlagsTy, 4> OutsFlags;
> + SmallVector<ISD::OutputArg, 4> Outs;
> SmallVector<uint64_t, 4> Offsets;
> - getReturnInfo(RetTy, CS.getAttributes().getRetAttributes(),
> - OutVTs, OutsFlags, TLI, &Offsets);
> + GetReturnInfo(RetTy, CS.getAttributes().getRetAttributes(),
> + Outs, TLI, &Offsets);
>
> bool CanLowerReturn = TLI.CanLowerReturn(CS.getCallingConv(),
> - FTy->isVarArg(), OutVTs, OutsFlags, FTy->getContext());
> + FTy->isVarArg(), Outs, FTy->getContext());
>
> SDValue DemoteStackSlot;
>
> @@ -4659,7 +4595,7 @@
> ComputeValueVTs(TLI, PtrRetTy, PVTs);
> assert(PVTs.size() == 1 && "Pointers should fit in one register");
> EVT PtrVT = PVTs[0];
> - unsigned NumValues = OutVTs.size();
> + unsigned NumValues = Outs.size();
> SmallVector<SDValue, 4> Values(NumValues);
> SmallVector<SDValue, 4> Chains(NumValues);
>
> @@ -4667,7 +4603,7 @@
> SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT,
> DemoteStackSlot,
> DAG.getConstant(Offsets[i], PtrVT));
> - SDValue L = DAG.getLoad(OutVTs[i], getCurDebugLoc(), Result.second,
> + SDValue L = DAG.getLoad(Outs[i].VT, getCurDebugLoc(), Result.second,
> Add, NULL, Offsets[i], false, false, 1);
> Values[i] = L;
> Chains[i] = L.getValue(1);
> @@ -5959,15 +5895,10 @@
> SmallVector<ISD::InputArg, 16> Ins;
>
> // Check whether the function can return without sret-demotion.
> - SmallVector<EVT, 4> OutVTs;
> - SmallVector<ISD::ArgFlagsTy, 4> OutsFlags;
> - getReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(),
> - OutVTs, OutsFlags, TLI);
> -
> - FuncInfo->CanLowerReturn = TLI.CanLowerReturn(F.getCallingConv(),
> - F.isVarArg(),
> - OutVTs, OutsFlags,
> - F.getContext());
> + SmallVector<ISD::OutputArg, 4> Outs;
> + GetReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(),
> + Outs, TLI);
> +
> if (!FuncInfo->CanLowerReturn) {
> // Put in an sret pointer parameter before all the other parameters.
> SmallVector<EVT, 1> ValueVTs;
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=107943&r1=107942&r2=107943&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Thu Jul 8 19:39:23 2010
> @@ -313,6 +313,26 @@
> // Determine if there is a call to setjmp in the machine function.
> MF->setCallsSetJmp(FunctionCallsSetJmp(&Fn));
>
> + // Replace forward-declared registers with the registers containing
> + // the desired value.
> + MachineRegisterInfo &MRI = MF->getRegInfo();
> + for (DenseMap<unsigned, unsigned>::iterator
> + I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end();
> + I != E; ++I) {
> + unsigned From = I->first;
> + unsigned To = I->second;
> + // If To is also scheduled to be replaced, find what its ultimate
> + // replacement is.
> + for (;;) {
> + DenseMap<unsigned, unsigned>::iterator J =
> + FuncInfo->RegFixups.find(To);
> + if (J == E) break;
> + To = J->second;
> + }
> + // Replace it.
> + MRI.replaceRegWith(From, To);
> + }
> +
> // Release function-specific state. SDB and CurDAG are already cleared
> // at this point.
> FuncInfo->clear();
> @@ -320,9 +340,8 @@
> return true;
> }
>
> -MachineBasicBlock *
> -SelectionDAGISel::SelectBasicBlock(MachineBasicBlock *BB,
> - BasicBlock::const_iterator Begin,
> +void
> +SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin,
> BasicBlock::const_iterator End,
> bool &HadTailCall) {
> // Lower all of the non-terminator instructions. If a call is emitted
> @@ -337,7 +356,7 @@
> SDB->clear();
>
> // Final step, emit the lowered DAG as machine code.
> - return CodeGenAndEmitDAG(BB);
> + CodeGenAndEmitDAG();
> }
>
> namespace {
> @@ -426,7 +445,7 @@
> } while (!Worklist.empty());
> }
>
> -MachineBasicBlock *SelectionDAGISel::CodeGenAndEmitDAG(MachineBasicBlock *BB) {
> +void SelectionDAGISel::CodeGenAndEmitDAG() {
> std::string GroupName;
> if (TimePassesIsEnabled)
> GroupName = "Instruction Selection and Scheduling";
> @@ -435,7 +454,7 @@
> ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
> ViewSUnitDAGs)
> BlockName = MF->getFunction()->getNameStr() + ":" +
> - BB->getBasicBlock()->getNameStr();
> + FuncInfo->MBB->getBasicBlock()->getNameStr();
>
> DEBUG(dbgs() << "Initial selection DAG:\n"; CurDAG->dump());
>
> @@ -542,7 +561,7 @@
> {
> NamedRegionTimer T("Instruction Scheduling", GroupName,
> TimePassesIsEnabled);
> - Scheduler->Run(CurDAG, BB, BB->end());
> + Scheduler->Run(CurDAG, FuncInfo->MBB, FuncInfo->InsertPt);
> }
>
> if (ViewSUnitDAGs) Scheduler->viewGraph();
> @@ -551,7 +570,9 @@
> // inserted into.
> {
> NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled);
> - BB = Scheduler->EmitSchedule();
> +
> + FuncInfo->MBB = Scheduler->EmitSchedule();
> + FuncInfo->InsertPt = Scheduler->InsertPos;
> }
>
> // Free the scheduler state.
> @@ -563,8 +584,6 @@
>
> // Free the SelectionDAG state, now that we're finished with it.
> CurDAG->clear();
> -
> - return BB;
> }
>
> void SelectionDAGISel::DoInstructionSelection() {
> @@ -626,21 +645,22 @@
>
> /// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and
> /// do other setup for EH landing-pad blocks.
> -void SelectionDAGISel::PrepareEHLandingPad(MachineBasicBlock *BB) {
> +void SelectionDAGISel::PrepareEHLandingPad() {
> // Add a label to mark the beginning of the landing pad. Deletion of the
> // landing pad can thus be detected via the MachineModuleInfo.
> - MCSymbol *Label = MF->getMMI().addLandingPad(BB);
> + MCSymbol *Label = MF->getMMI().addLandingPad(FuncInfo->MBB);
>
> const TargetInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL);
> - BuildMI(BB, SDB->getCurDebugLoc(), II).addSym(Label);
> + BuildMI(*FuncInfo->MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II)
> + .addSym(Label);
>
> // Mark exception register as live in.
> unsigned Reg = TLI.getExceptionAddressRegister();
> - if (Reg) BB->addLiveIn(Reg);
> + if (Reg) FuncInfo->MBB->addLiveIn(Reg);
>
> // Mark exception selector register as live in.
> Reg = TLI.getExceptionSelectorRegister();
> - if (Reg) BB->addLiveIn(Reg);
> + if (Reg) FuncInfo->MBB->addLiveIn(Reg);
>
> // FIXME: Hack around an exception handling flaw (PR1508): the personality
> // function and list of typeids logically belong to the invoke (or, if you
> @@ -653,7 +673,7 @@
> // in exceptions not being caught because no typeids are associated with
> // the invoke. This may not be the only way things can go wrong, but it
> // is the only way we try to work around for the moment.
> - const BasicBlock *LLVMBB = BB->getBasicBlock();
> + const BasicBlock *LLVMBB = FuncInfo->MBB->getBasicBlock();
> const BranchInst *Br = dyn_cast<BranchInst>(LLVMBB->getTerminator());
>
> if (Br && Br->isUnconditional()) { // Critical edge?
> @@ -677,80 +697,95 @@
> // Iterate over all basic blocks in the function.
> for (Function::const_iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) {
> const BasicBlock *LLVMBB = &*I;
> - MachineBasicBlock *BB = FuncInfo->MBBMap[LLVMBB];
> + FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB];
> + FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
>
> BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI();
> BasicBlock::const_iterator const End = LLVMBB->end();
> - BasicBlock::const_iterator BI = Begin;
> + BasicBlock::const_iterator BI = End;
> +
> + FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
>
> + // Setup an EH landing-pad block.
> + if (FuncInfo->MBB->isLandingPad())
> + PrepareEHLandingPad();
> +
> // Lower any arguments needed in this block if this is the entry block.
> if (LLVMBB == &Fn.getEntryBlock())
> LowerArguments(LLVMBB);
>
> - // Setup an EH landing-pad block.
> - if (BB->isLandingPad())
> - PrepareEHLandingPad(BB);
> -
> // Before doing SelectionDAG ISel, see if FastISel has been requested.
> if (FastIS) {
> + FastIS->startNewBlock();
> +
> // Emit code for any incoming arguments. This must happen before
> // beginning FastISel on the entry block.
> if (LLVMBB == &Fn.getEntryBlock()) {
> CurDAG->setRoot(SDB->getControlRoot());
> SDB->clear();
> - BB = CodeGenAndEmitDAG(BB);
> + CodeGenAndEmitDAG();
> +
> + // If we inserted any instructions at the beginning, make a note of
> + // where they are, so we can be sure to emit subsequent instructions
> + // after them.
> + if (FuncInfo->InsertPt != FuncInfo->MBB->begin())
> + FastIS->setLastLocalValue(llvm::prior(FuncInfo->InsertPt));
> + else
> + FastIS->setLastLocalValue(0);
> }
> - FastIS->startNewBlock(BB);
> +
> // Do FastISel on as many instructions as possible.
> - for (; BI != End; ++BI) {
> -#if 0
> - // Defer instructions with no side effects; they'll be emitted
> - // on-demand later.
> - if (BI->isSafeToSpeculativelyExecute() &&
> - !FuncInfo->isExportedInst(BI))
> + for (; BI != Begin; --BI) {
> + const Instruction *Inst = llvm::prior(BI);
> +
> + // If we no longer require this instruction, skip it.
> + if (!Inst->mayWriteToMemory() &&
> + !isa<TerminatorInst>(Inst) &&
> + !isa<DbgInfoIntrinsic>(Inst) &&
> + !FuncInfo->isExportedInst(Inst))
> continue;
> -#endif
> +
> + // Bottom-up: reset the insert pos at the top, after any local-value
> + // instructions.
> + FastIS->recomputeInsertPt();
>
> // Try to select the instruction with FastISel.
> - if (FastIS->SelectInstruction(BI))
> + if (FastIS->SelectInstruction(Inst))
> continue;
>
> // Then handle certain instructions as single-LLVM-Instruction blocks.
> - if (isa<CallInst>(BI)) {
> + if (isa<CallInst>(Inst)) {
> ++NumFastIselFailures;
> if (EnableFastISelVerbose || EnableFastISelAbort) {
> dbgs() << "FastISel missed call: ";
> - BI->dump();
> + Inst->dump();
> }
>
> - if (!BI->getType()->isVoidTy() && !BI->use_empty()) {
> - unsigned &R = FuncInfo->ValueMap[BI];
> + if (!Inst->getType()->isVoidTy() && !Inst->use_empty()) {
> + unsigned &R = FuncInfo->ValueMap[Inst];
> if (!R)
> - R = FuncInfo->CreateRegs(BI->getType());
> + R = FuncInfo->CreateRegs(Inst->getType());
> }
>
> bool HadTailCall = false;
> - BB = SelectBasicBlock(BB, BI, llvm::next(BI), HadTailCall);
> + SelectBasicBlock(Inst, BI, HadTailCall);
>
> // If the call was emitted as a tail call, we're done with the block.
> if (HadTailCall) {
> - BI = End;
> + --BI;
> break;
> }
>
> - // If the instruction was codegen'd with multiple blocks,
> - // inform the FastISel object where to resume inserting.
> - FastIS->setCurrentBlock(BB);
> continue;
> }
>
> // Otherwise, give up on FastISel for the rest of the block.
> // For now, be a little lenient about non-branch terminators.
> - if (!isa<TerminatorInst>(BI) || isa<BranchInst>(BI)) {
> + if (!isa<TerminatorInst>(Inst) || isa<BranchInst>(Inst)) {
> ++NumFastIselFailures;
> if (EnableFastISelVerbose || EnableFastISelAbort) {
> dbgs() << "FastISel miss: ";
> - BI->dump();
> + Inst->dump();
> }
> if (EnableFastISelAbort)
> // The "fast" selector couldn't handle something and bailed.
> @@ -759,17 +794,17 @@
> }
> break;
> }
> +
> + FastIS->recomputeInsertPt();
> }
>
> // Run SelectionDAG instruction selection on the remainder of the block
> // not handled by FastISel. If FastISel is not run, this is the entire
> // block.
> - if (BI != End) {
> - bool HadTailCall;
> - BB = SelectBasicBlock(BB, BI, End, HadTailCall);
> - }
> + bool HadTailCall;
> + SelectBasicBlock(Begin, BI, HadTailCall);
>
> - FinishBasicBlock(BB);
> + FinishBasicBlock();
> FuncInfo->PHINodesToUpdate.clear();
> }
>
> @@ -777,7 +812,7 @@
> }
>
> void
> -SelectionDAGISel::FinishBasicBlock(MachineBasicBlock *BB) {
> +SelectionDAGISel::FinishBasicBlock() {
>
> DEBUG(dbgs() << "Total amount of phi nodes to update: "
> << FuncInfo->PHINodesToUpdate.size() << "\n";
> @@ -795,11 +830,11 @@
> MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first;
> assert(PHI->isPHI() &&
> "This is not a machine PHI node that we are updating!");
> - if (!BB->isSuccessor(PHI->getParent()))
> + if (!FuncInfo->MBB->isSuccessor(PHI->getParent()))
> continue;
> PHI->addOperand(
> MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false));
> - PHI->addOperand(MachineOperand::CreateMBB(BB));
> + PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB));
> }
> return;
> }
> @@ -808,33 +843,35 @@
> // Lower header first, if it wasn't already lowered
> if (!SDB->BitTestCases[i].Emitted) {
> // Set the current basic block to the mbb we wish to insert the code into
> - BB = SDB->BitTestCases[i].Parent;
> + FuncInfo->MBB = SDB->BitTestCases[i].Parent;
> + FuncInfo->InsertPt = FuncInfo->MBB->end();
> // Emit the code
> - SDB->visitBitTestHeader(SDB->BitTestCases[i], BB);
> + SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB);
> CurDAG->setRoot(SDB->getRoot());
> SDB->clear();
> - BB = CodeGenAndEmitDAG(BB);
> + CodeGenAndEmitDAG();
> }
>
> for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
> // Set the current basic block to the mbb we wish to insert the code into
> - BB = SDB->BitTestCases[i].Cases[j].ThisBB;
> + FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB;
> + FuncInfo->InsertPt = FuncInfo->MBB->end();
> // Emit the code
> if (j+1 != ej)
> SDB->visitBitTestCase(SDB->BitTestCases[i].Cases[j+1].ThisBB,
> SDB->BitTestCases[i].Reg,
> SDB->BitTestCases[i].Cases[j],
> - BB);
> + FuncInfo->MBB);
> else
> SDB->visitBitTestCase(SDB->BitTestCases[i].Default,
> SDB->BitTestCases[i].Reg,
> SDB->BitTestCases[i].Cases[j],
> - BB);
> + FuncInfo->MBB);
>
>
> CurDAG->setRoot(SDB->getRoot());
> SDB->clear();
> - BB = CodeGenAndEmitDAG(BB);
> + CodeGenAndEmitDAG();
> }
>
> // Update PHI Nodes
> @@ -879,22 +916,24 @@
> // Lower header first, if it wasn't already lowered
> if (!SDB->JTCases[i].first.Emitted) {
> // Set the current basic block to the mbb we wish to insert the code into
> - BB = SDB->JTCases[i].first.HeaderBB;
> + FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB;
> + FuncInfo->InsertPt = FuncInfo->MBB->end();
> // Emit the code
> SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first,
> - BB);
> + FuncInfo->MBB);
> CurDAG->setRoot(SDB->getRoot());
> SDB->clear();
> - BB = CodeGenAndEmitDAG(BB);
> + CodeGenAndEmitDAG();
> }
>
> // Set the current basic block to the mbb we wish to insert the code into
> - BB = SDB->JTCases[i].second.MBB;
> + FuncInfo->MBB = SDB->JTCases[i].second.MBB;
> + FuncInfo->InsertPt = FuncInfo->MBB->end();
> // Emit the code
> SDB->visitJumpTable(SDB->JTCases[i].second);
> CurDAG->setRoot(SDB->getRoot());
> SDB->clear();
> - BB = CodeGenAndEmitDAG(BB);
> + CodeGenAndEmitDAG();
>
> // Update PHI Nodes
> for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
> @@ -912,11 +951,11 @@
> (MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB));
> }
> // JT BB. Just iterate over successors here
> - if (BB->isSuccessor(PHIBB)) {
> + if (FuncInfo->MBB->isSuccessor(PHIBB)) {
> PHI->addOperand
> (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
> false));
> - PHI->addOperand(MachineOperand::CreateMBB(BB));
> + PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB));
> }
> }
> }
> @@ -928,10 +967,10 @@
> MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first;
> assert(PHI->isPHI() &&
> "This is not a machine PHI node that we are updating!");
> - if (BB->isSuccessor(PHI->getParent())) {
> + if (FuncInfo->MBB->isSuccessor(PHI->getParent())) {
> PHI->addOperand(
> MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false));
> - PHI->addOperand(MachineOperand::CreateMBB(BB));
> + PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB));
> }
> }
>
> @@ -939,7 +978,8 @@
> // additional DAGs necessary.
> for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
> // Set the current basic block to the mbb we wish to insert the code into
> - MachineBasicBlock *ThisBB = BB = SDB->SwitchCases[i].ThisBB;
> + MachineBasicBlock *ThisBB = FuncInfo->MBB = SDB->SwitchCases[i].ThisBB;
> + FuncInfo->InsertPt = FuncInfo->MBB->end();
>
> // Determine the unique successors.
> SmallVector<MachineBasicBlock *, 2> Succs;
> @@ -949,21 +989,24 @@
>
> // Emit the code. Note that this could result in ThisBB being split, so
> // we need to check for updates.
> - SDB->visitSwitchCase(SDB->SwitchCases[i], BB);
> + SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB);
> CurDAG->setRoot(SDB->getRoot());
> SDB->clear();
> - ThisBB = CodeGenAndEmitDAG(BB);
> + CodeGenAndEmitDAG();
> + ThisBB = FuncInfo->MBB;
>
> // Handle any PHI nodes in successors of this chunk, as if we were coming
> // from the original BB before switch expansion. Note that PHI nodes can
> // occur multiple times in PHINodesToUpdate. We have to be very careful to
> // handle them the right number of times.
> for (unsigned i = 0, e = Succs.size(); i != e; ++i) {
> - BB = Succs[i];
> - // BB may have been removed from the CFG if a branch was constant folded.
> - if (ThisBB->isSuccessor(BB)) {
> - for (MachineBasicBlock::iterator Phi = BB->begin();
> - Phi != BB->end() && Phi->isPHI();
> + FuncInfo->MBB = Succs[i];
> + FuncInfo->InsertPt = FuncInfo->MBB->end();
> + // FuncInfo->MBB may have been removed from the CFG if a branch was
> + // constant folded.
> + if (ThisBB->isSuccessor(FuncInfo->MBB)) {
> + for (MachineBasicBlock::iterator Phi = FuncInfo->MBB->begin();
> + Phi != FuncInfo->MBB->end() && Phi->isPHI();
> ++Phi) {
> // This value for this PHI node is recorded in PHINodesToUpdate.
> for (unsigned pn = 0; ; ++pn) {
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=107943&r1=107942&r2=107943&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Thu Jul 8 19:39:23 2010
> @@ -20,6 +20,7 @@
> #include "llvm/Target/TargetRegisterInfo.h"
> #include "llvm/GlobalVariable.h"
> #include "llvm/DerivedTypes.h"
> +#include "llvm/CodeGen/Analysis.h"
> #include "llvm/CodeGen/MachineFrameInfo.h"
> #include "llvm/CodeGen/MachineJumpTableInfo.h"
> #include "llvm/CodeGen/MachineFunction.h"
> @@ -838,6 +839,65 @@
> return 1;
> }
>
> +/// Get the EVTs and ArgFlags collections that represent the legalized return
> +/// type of the given function. This does not require a DAG or a return value,
> +/// and is suitable for use before any DAGs for the function are constructed.
> +/// TODO: Move this out of TargetLowering.cpp.
> +void llvm::GetReturnInfo(const Type* ReturnType, Attributes attr,
> + SmallVectorImpl<ISD::OutputArg> &Outs,
> + const TargetLowering &TLI,
> + SmallVectorImpl<uint64_t> *Offsets) {
> + SmallVector<EVT, 4> ValueVTs;
> + ComputeValueVTs(TLI, ReturnType, ValueVTs);
> + unsigned NumValues = ValueVTs.size();
> + if (NumValues == 0) return;
> + unsigned Offset = 0;
> +
> + for (unsigned j = 0, f = NumValues; j != f; ++j) {
> + EVT VT = ValueVTs[j];
> + ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
> +
> + if (attr & Attribute::SExt)
> + ExtendKind = ISD::SIGN_EXTEND;
> + else if (attr & Attribute::ZExt)
> + ExtendKind = ISD::ZERO_EXTEND;
> +
> + // FIXME: C calling convention requires the return type to be promoted to
> + // at least 32-bit. But this is not necessary for non-C calling
> + // conventions. The frontend should mark functions whose return values
> + // require promoting with signext or zeroext attributes.
> + if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
> + EVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32);
> + if (VT.bitsLT(MinVT))
> + VT = MinVT;
> + }
> +
> + unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT);
> + EVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT);
> + unsigned PartSize = TLI.getTargetData()->getTypeAllocSize(
> + PartVT.getTypeForEVT(ReturnType->getContext()));
> +
> + // 'inreg' on function refers to return value
> + ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
> + if (attr & Attribute::InReg)
> + Flags.setInReg();
> +
> + // Propagate extension type if any
> + if (attr & Attribute::SExt)
> + Flags.setSExt();
> + else if (attr & Attribute::ZExt)
> + Flags.setZExt();
> +
> + for (unsigned i = 0; i < NumParts; ++i) {
> + Outs.push_back(ISD::OutputArg(Flags, PartVT, /*isFixed=*/true));
> + if (Offsets) {
> + Offsets->push_back(Offset);
> + Offset += PartSize;
> + }
> + }
> + }
> +}
> +
> /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
> /// function arguments in the caller parameter area. This is the actual
> /// alignment, not its logarithm.
>
> Modified: llvm/trunk/lib/Target/X86/X86FastISel.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FastISel.cpp?rev=107943&r1=107942&r2=107943&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86FastISel.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86FastISel.cpp Thu Jul 8 19:39:23 2010
> @@ -23,6 +23,7 @@
> #include "llvm/GlobalVariable.h"
> #include "llvm/Instructions.h"
> #include "llvm/IntrinsicInst.h"
> +#include "llvm/CodeGen/Analysis.h"
> #include "llvm/CodeGen/FastISel.h"
> #include "llvm/CodeGen/FunctionLoweringInfo.h"
> #include "llvm/CodeGen/MachineConstantPool.h"
> @@ -84,6 +85,8 @@
>
> bool X86SelectStore(const Instruction *I);
>
> + bool X86SelectRet(const Instruction *I);
> +
> bool X86SelectCmp(const Instruction *I);
>
> bool X86SelectZExt(const Instruction *I);
> @@ -105,6 +108,7 @@
> bool X86SelectCall(const Instruction *I);
>
> CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool isTailCall = false);
> + CCAssignFn *CCAssignFnForRet(CallingConv::ID CC, bool isTailCall = false);
>
> const X86InstrInfo *getInstrInfo() const {
> return getTargetMachine()->getInstrInfo();
> @@ -178,6 +182,20 @@
> return CC_X86_32_C;
> }
>
> +/// CCAssignFnForRet - Selects the correct CCAssignFn for a given calling
> +/// convention.
> +CCAssignFn *X86FastISel::CCAssignFnForRet(CallingConv::ID CC,
> + bool isTaillCall) {
> + if (Subtarget->is64Bit()) {
> + if (Subtarget->isTargetWin64())
> + return RetCC_X86_Win64_C;
> + else
> + return RetCC_X86_64_C;
> + }
> +
> + return RetCC_X86_32_C;
> +}
> +
> /// X86FastEmitLoad - Emit a machine instruction to load a value of type VT.
> /// The address is either pre-computed, i.e. Ptr, or a GlobalAddress, i.e. GV.
> /// Return true and the result register by reference if it is possible.
> @@ -230,7 +248,8 @@
> }
>
> ResultReg = createResultReg(RC);
> - addFullAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), AM);
> + addFullAddress(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
> + DL, TII.get(Opc), ResultReg), AM);
> return true;
> }
>
> @@ -249,7 +268,7 @@
> case MVT::i1: {
> // Mask out all but lowest bit.
> unsigned AndResult = createResultReg(X86::GR8RegisterClass);
> - BuildMI(MBB, DL,
> + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
> TII.get(X86::AND8ri), AndResult).addReg(Val).addImm(1);
> Val = AndResult;
> }
> @@ -266,7 +285,8 @@
> break;
> }
>
> - addFullAddress(BuildMI(MBB, DL, TII.get(Opc)), AM).addReg(Val);
> + addFullAddress(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
> + DL, TII.get(Opc)), AM).addReg(Val);
> return true;
> }
>
> @@ -294,7 +314,8 @@
> }
>
> if (Opc) {
> - addFullAddress(BuildMI(MBB, DL, TII.get(Opc)), AM)
> + addFullAddress(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
> + DL, TII.get(Opc)), AM)
> .addImm(Signed ? (uint64_t) CI->getSExtValue() :
> CI->getZExtValue());
> return true;
> @@ -333,7 +354,7 @@
> // Don't walk into other basic blocks; it's possible we haven't
> // visited them yet, so the instructions may not yet be assigned
> // virtual registers.
> - if (FuncInfo.MBBMap[I->getParent()] != MBB)
> + if (FuncInfo.MBBMap[I->getParent()] != FuncInfo.MBB)
> return false;
>
> Opcode = I->getOpcode();
> @@ -518,6 +539,9 @@
> StubAM.GV = GV;
> StubAM.GVOpFlags = GVFlags;
>
> + // Prepare for inserting code in the local-value area.
> + MachineBasicBlock::iterator SaveInsertPt = enterLocalValueArea();
> +
> if (TLI.getPointerTy() == MVT::i64) {
> Opc = X86::MOV64rm;
> RC = X86::GR64RegisterClass;
> @@ -530,8 +554,13 @@
> }
>
> LoadReg = createResultReg(RC);
> - addFullAddress(BuildMI(MBB, DL, TII.get(Opc), LoadReg), StubAM);
> -
> + MachineInstrBuilder LoadMI =
> + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), LoadReg);
> + addFullAddress(LoadMI, StubAM);
> +
> + // Ok, back to normal mode.
> + leaveLocalValueArea(SaveInsertPt);
> +
> // Prevent loading GV stub multiple times in same MBB.
> LocalValueMap[V] = LoadReg;
> }
> @@ -656,6 +685,76 @@
> return X86FastEmitStore(VT, I->getOperand(0), AM);
> }
>
> +/// X86SelectRet - Select and emit code to implement ret instructions.
> +bool X86FastISel::X86SelectRet(const Instruction *I) {
> + const ReturnInst *Ret = cast<ReturnInst>(I);
> + const Function &F = *I->getParent()->getParent();
> +
> + if (!FuncInfo.CanLowerReturn)
> + return false;
> +
> + CallingConv::ID CC = F.getCallingConv();
> + if (CC != CallingConv::C &&
> + CC != CallingConv::Fast &&
> + CC != CallingConv::X86_FastCall)
> + return false;
> +
> + if (Subtarget->isTargetWin64())
> + return false;
> +
> + // fastcc with -tailcallopt is intended to provide a guaranteed
> + // tail call optimization. Fastisel doesn't know how to do that.
> + if (CC == CallingConv::Fast && GuaranteedTailCallOpt)
> + return false;
> +
> + // Let SDISel handle vararg functions.
> + if (F.isVarArg())
> + return false;
> +
> + if (Ret->getNumOperands() > 0) {
> + SmallVector<ISD::OutputArg, 4> Outs;
> + GetReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(),
> + Outs, TLI);
> +
> + // Analyze operands of the call, assigning locations to each operand.
> + SmallVector<CCValAssign, 16> ValLocs;
> + CCState CCInfo(CC, F.isVarArg(), TM, ValLocs, I->getContext());
> + CCInfo.AnalyzeReturn(Outs, CCAssignFnForRet(CC));
> +
> + const Value *RV = Ret->getOperand(0);
> + unsigned Reg = getRegForValue(RV);
> + if (Reg == 0)
> + return false;
> +
> + // Copy the return value into registers.
> + for (unsigned i = 0, e = ValLocs.size(); i != e; ++i) {
> + CCValAssign &VA = ValLocs[i];
> +
> + // Don't bother handling odd stuff for now.
> + if (VA.getLocInfo() != CCValAssign::Full)
> + return false;
> + if (!VA.isRegLoc())
> + return false;
> + // TODO: For now, don't try to handle cases where getLocInfo()
> + // says Full but the types don't match.
> + if (VA.getValVT() != TLI.getValueType(RV->getType()))
> + return false;
> +
> + TargetRegisterClass* RC = TLI.getRegClassFor(VA.getValVT());
> + bool Emitted = TII.copyRegToReg(*FuncInfo.MBB, FuncInfo.InsertPt,
> + VA.getLocReg(), Reg + VA.getValNo(),
> + RC, RC, DL);
> + assert(Emitted && "Failed to emit a copy instruction!"); Emitted=Emitted;
> +
> + MRI.addLiveOut(VA.getLocReg());
> + }
> + }
> +
> + // Now emit the RET.
> + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::RET));
> + return true;
> +}
> +
> /// X86SelectLoad - Select and emit code to implement load instructions.
> ///
> bool X86FastISel::X86SelectLoad(const Instruction *I) {
> @@ -720,8 +819,9 @@
> // CMPri, otherwise use CMPrr.
> if (const ConstantInt *Op1C = dyn_cast<ConstantInt>(Op1)) {
> if (unsigned CompareImmOpc = X86ChooseCmpImmediateOpcode(VT, Op1C)) {
> - BuildMI(MBB, DL, TII.get(CompareImmOpc)).addReg(Op0Reg)
> - .addImm(Op1C->getSExtValue());
> + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CompareImmOpc))
> + .addReg(Op0Reg)
> + .addImm(Op1C->getSExtValue());
> return true;
> }
> }
> @@ -731,7 +831,9 @@
>
> unsigned Op1Reg = getRegForValue(Op1);
> if (Op1Reg == 0) return false;
> - BuildMI(MBB, DL, TII.get(CompareOpc)).addReg(Op0Reg).addReg(Op1Reg);
> + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CompareOpc))
> + .addReg(Op0Reg)
> + .addReg(Op1Reg);
>
> return true;
> }
> @@ -753,9 +855,10 @@
>
> unsigned EReg = createResultReg(&X86::GR8RegClass);
> unsigned NPReg = createResultReg(&X86::GR8RegClass);
> - BuildMI(MBB, DL, TII.get(X86::SETEr), EReg);
> - BuildMI(MBB, DL, TII.get(X86::SETNPr), NPReg);
> - BuildMI(MBB, DL,
> + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::SETEr), EReg);
> + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
> + TII.get(X86::SETNPr), NPReg);
> + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
> TII.get(X86::AND8rr), ResultReg).addReg(NPReg).addReg(EReg);
> UpdateValueMap(I, ResultReg);
> return true;
> @@ -766,9 +869,13 @@
>
> unsigned NEReg = createResultReg(&X86::GR8RegClass);
> unsigned PReg = createResultReg(&X86::GR8RegClass);
> - BuildMI(MBB, DL, TII.get(X86::SETNEr), NEReg);
> - BuildMI(MBB, DL, TII.get(X86::SETPr), PReg);
> - BuildMI(MBB, DL, TII.get(X86::OR8rr), ResultReg).addReg(PReg).addReg(NEReg);
> + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
> + TII.get(X86::SETNEr), NEReg);
> + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
> + TII.get(X86::SETPr), PReg);
> + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
> + TII.get(X86::OR8rr), ResultReg)
> + .addReg(PReg).addReg(NEReg);
> UpdateValueMap(I, ResultReg);
> return true;
> }
> @@ -807,7 +914,7 @@
> if (!X86FastEmitCompare(Op0, Op1, VT))
> return false;
>
> - BuildMI(MBB, DL, TII.get(SetCCOpc), ResultReg);
> + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(SetCCOpc), ResultReg);
> UpdateValueMap(I, ResultReg);
> return true;
> }
> @@ -843,7 +950,7 @@
>
> // Try to take advantage of fallthrough opportunities.
> CmpInst::Predicate Predicate = CI->getPredicate();
> - if (MBB->isLayoutSuccessor(TrueMBB)) {
> + if (FuncInfo.MBB->isLayoutSuccessor(TrueMBB)) {
> std::swap(TrueMBB, FalseMBB);
> Predicate = CmpInst::getInversePredicate(Predicate);
> }
> @@ -892,16 +999,18 @@
> if (!X86FastEmitCompare(Op0, Op1, VT))
> return false;
>
> - BuildMI(MBB, DL, TII.get(BranchOpc)).addMBB(TrueMBB);
> + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BranchOpc))
> + .addMBB(TrueMBB);
>
> if (Predicate == CmpInst::FCMP_UNE) {
> // X86 requires a second branch to handle UNE (and OEQ,
> // which is mapped to UNE above).
> - BuildMI(MBB, DL, TII.get(X86::JP_4)).addMBB(TrueMBB);
> + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::JP_4))
> + .addMBB(TrueMBB);
> }
>
> FastEmitBranch(FalseMBB, DL);
> - MBB->addSuccessor(TrueMBB);
> + FuncInfo.MBB->addSuccessor(TrueMBB);
> return true;
> }
> } else if (ExtractValueInst *EI =
> @@ -927,7 +1036,8 @@
> unsigned Reg = getRegForValue(EI);
>
> for (MachineBasicBlock::const_reverse_iterator
> - RI = MBB->rbegin(), RE = MBB->rend(); RI != RE; ++RI) {
> + RI = FuncInfo.MBB->rbegin(), RE = FuncInfo.MBB->rend();
> + RI != RE; ++RI) {
> const MachineInstr &MI = *RI;
>
> if (MI.definesRegister(Reg)) {
> @@ -952,11 +1062,11 @@
> unsigned OpCode = SetMI->getOpcode();
>
> if (OpCode == X86::SETOr || OpCode == X86::SETBr) {
> - BuildMI(MBB, DL, TII.get(OpCode == X86::SETOr ?
> - X86::JO_4 : X86::JB_4))
> + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
> + TII.get(OpCode == X86::SETOr ? X86::JO_4 : X86::JB_4))
> .addMBB(TrueMBB);
> FastEmitBranch(FalseMBB, DL);
> - MBB->addSuccessor(TrueMBB);
> + FuncInfo.MBB->addSuccessor(TrueMBB);
> return true;
> }
> }
> @@ -968,10 +1078,12 @@
> unsigned OpReg = getRegForValue(BI->getCondition());
> if (OpReg == 0) return false;
>
> - BuildMI(MBB, DL, TII.get(X86::TEST8rr)).addReg(OpReg).addReg(OpReg);
> - BuildMI(MBB, DL, TII.get(X86::JNE_4)).addMBB(TrueMBB);
> + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::TEST8rr))
> + .addReg(OpReg).addReg(OpReg);
> + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::JNE_4))
> + .addMBB(TrueMBB);
> FastEmitBranch(FalseMBB, DL);
> - MBB->addSuccessor(TrueMBB);
> + FuncInfo.MBB->addSuccessor(TrueMBB);
> return true;
> }
>
> @@ -1028,7 +1140,7 @@
> // Fold immediate in shl(x,3).
> if (const ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) {
> unsigned ResultReg = createResultReg(RC);
> - BuildMI(MBB, DL, TII.get(OpImm),
> + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(OpImm),
> ResultReg).addReg(Op0Reg).addImm(CI->getZExtValue() & 0xff);
> UpdateValueMap(I, ResultReg);
> return true;
> @@ -1036,16 +1148,19 @@
>
> unsigned Op1Reg = getRegForValue(I->getOperand(1));
> if (Op1Reg == 0) return false;
> - TII.copyRegToReg(*MBB, MBB->end(), CReg, Op1Reg, RC, RC, DL);
> + TII.copyRegToReg(*FuncInfo.MBB, FuncInfo.InsertPt,
> + CReg, Op1Reg, RC, RC, DL);
>
> // The shift instruction uses X86::CL. If we defined a super-register
> // of X86::CL, emit a subreg KILL to precisely describe what we're doing here.
> if (CReg != X86::CL)
> - BuildMI(MBB, DL, TII.get(TargetOpcode::KILL), X86::CL)
> + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
> + TII.get(TargetOpcode::KILL), X86::CL)
> .addReg(CReg, RegState::Kill);
>
> unsigned ResultReg = createResultReg(RC);
> - BuildMI(MBB, DL, TII.get(OpReg), ResultReg).addReg(Op0Reg);
> + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(OpReg), ResultReg)
> + .addReg(Op0Reg);
> UpdateValueMap(I, ResultReg);
> return true;
> }
> @@ -1077,9 +1192,11 @@
> unsigned Op2Reg = getRegForValue(I->getOperand(2));
> if (Op2Reg == 0) return false;
>
> - BuildMI(MBB, DL, TII.get(X86::TEST8rr)).addReg(Op0Reg).addReg(Op0Reg);
> + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::TEST8rr))
> + .addReg(Op0Reg).addReg(Op0Reg);
> unsigned ResultReg = createResultReg(RC);
> - BuildMI(MBB, DL, TII.get(Opc), ResultReg).addReg(Op1Reg).addReg(Op2Reg);
> + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), ResultReg)
> + .addReg(Op1Reg).addReg(Op2Reg);
> UpdateValueMap(I, ResultReg);
> return true;
> }
> @@ -1093,7 +1210,9 @@
> unsigned OpReg = getRegForValue(V);
> if (OpReg == 0) return false;
> unsigned ResultReg = createResultReg(X86::FR64RegisterClass);
> - BuildMI(MBB, DL, TII.get(X86::CVTSS2SDrr), ResultReg).addReg(OpReg);
> + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
> + TII.get(X86::CVTSS2SDrr), ResultReg)
> + .addReg(OpReg);
> UpdateValueMap(I, ResultReg);
> return true;
> }
> @@ -1110,7 +1229,9 @@
> unsigned OpReg = getRegForValue(V);
> if (OpReg == 0) return false;
> unsigned ResultReg = createResultReg(X86::FR32RegisterClass);
> - BuildMI(MBB, DL, TII.get(X86::CVTSD2SSrr), ResultReg).addReg(OpReg);
> + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
> + TII.get(X86::CVTSD2SSrr), ResultReg)
> + .addReg(OpReg);
> UpdateValueMap(I, ResultReg);
> return true;
> }
> @@ -1145,7 +1266,8 @@
> const TargetRegisterClass *CopyRC = (SrcVT == MVT::i16)
> ? X86::GR16_ABCDRegisterClass : X86::GR32_ABCDRegisterClass;
> unsigned CopyReg = createResultReg(CopyRC);
> - BuildMI(MBB, DL, TII.get(CopyOpc), CopyReg).addReg(InputReg);
> + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CopyOpc), CopyReg)
> + .addReg(InputReg);
>
> // Then issue an extract_subreg.
> unsigned ResultReg = FastEmitInst_extractsubreg(MVT::i8,
> @@ -1166,14 +1288,18 @@
> switch (CI->getIntrinsicID()) {
> default: break;
> case Intrinsic::sadd_with_overflow:
> - case Intrinsic::uadd_with_overflow:
> + case Intrinsic::uadd_with_overflow: {
> // Cheat a little. We know that the registers for "add" and "seto" are
> // allocated sequentially. However, we only keep track of the register
> // for "add" in the value map. Use extractvalue's index to get the
> // correct register for "seto".
> - UpdateValueMap(I, lookUpRegForValue(Agg) + *EI->idx_begin());
> + unsigned OpReg = getRegForValue(Agg);
> + if (OpReg == 0)
> + return false;
> + UpdateValueMap(I, OpReg + *EI->idx_begin());
> return true;
> }
> + }
> }
>
> return false;
> @@ -1217,7 +1343,7 @@
> return false;
>
> unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
> - BuildMI(MBB, DL, TII.get(OpC), ResultReg).
> + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(OpC), ResultReg).
> addImm(CI->isZero() ? -1ULL : 0);
> UpdateValueMap(&I, ResultReg);
> return true;
> @@ -1231,12 +1357,12 @@
> const TargetInstrDesc &II = TII.get(TargetOpcode::DBG_VALUE);
> // FIXME may need to add RegState::Debug to any registers produced,
> // although ESP/EBP should be the only ones at the moment.
> - addFullAddress(BuildMI(MBB, DL, II), AM).addImm(0).
> - addMetadata(DI->getVariable());
> + addFullAddress(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II), AM).
> + addImm(0).addMetadata(DI->getVariable());
> return true;
> }
> case Intrinsic::trap: {
> - BuildMI(MBB, DL, TII.get(X86::TRAP));
> + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::TRAP));
> return true;
> }
> case Intrinsic::sadd_with_overflow:
> @@ -1272,7 +1398,8 @@
> return false;
>
> unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
> - BuildMI(MBB, DL, TII.get(OpC), ResultReg).addReg(Reg1).addReg(Reg2);
> + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(OpC), ResultReg)
> + .addReg(Reg1).addReg(Reg2);
> unsigned DestReg1 = UpdateValueMap(&I, ResultReg);
>
> // If the add with overflow is an intra-block value then we just want to
> @@ -1290,7 +1417,7 @@
> unsigned Opc = X86::SETBr;
> if (I.getIntrinsicID() == Intrinsic::sadd_with_overflow)
> Opc = X86::SETOr;
> - BuildMI(MBB, DL, TII.get(Opc), ResultReg);
> + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), ResultReg);
> return true;
> }
> }
> @@ -1417,7 +1544,8 @@
>
> // Issue CALLSEQ_START
> unsigned AdjStackDown = TM.getRegisterInfo()->getCallFrameSetupOpcode();
> - BuildMI(MBB, DL, TII.get(AdjStackDown)).addImm(NumBytes);
> + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(AdjStackDown))
> + .addImm(NumBytes);
>
> // Process argument: walk the register/memloc assignments, inserting
> // copies / loads.
> @@ -1473,8 +1601,8 @@
>
> if (VA.isRegLoc()) {
> TargetRegisterClass* RC = TLI.getRegClassFor(ArgVT);
> - bool Emitted = TII.copyRegToReg(*MBB, MBB->end(), VA.getLocReg(),
> - Arg, RC, RC, DL);
> + bool Emitted = TII.copyRegToReg(*FuncInfo.MBB, FuncInfo.InsertPt,
> + VA.getLocReg(), Arg, RC, RC, DL);
> assert(Emitted && "Failed to emit a copy instruction!"); Emitted=Emitted;
> Emitted = true;
> RegArgs.push_back(VA.getLocReg());
> @@ -1500,8 +1628,8 @@
> if (Subtarget->isPICStyleGOT()) {
> TargetRegisterClass *RC = X86::GR32RegisterClass;
> unsigned Base = getInstrInfo()->getGlobalBaseReg(FuncInfo.MF);
> - bool Emitted = TII.copyRegToReg(*MBB, MBB->end(), X86::EBX, Base, RC, RC,
> - DL);
> + bool Emitted = TII.copyRegToReg(*FuncInfo.MBB, FuncInfo.InsertPt,
> + X86::EBX, Base, RC, RC, DL);
> assert(Emitted && "Failed to emit a copy instruction!"); Emitted=Emitted;
> Emitted = true;
> }
> @@ -1511,7 +1639,8 @@
> if (CalleeOp) {
> // Register-indirect call.
> unsigned CallOpc = Subtarget->is64Bit() ? X86::CALL64r : X86::CALL32r;
> - MIB = BuildMI(MBB, DL, TII.get(CallOpc)).addReg(CalleeOp);
> + MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CallOpc))
> + .addReg(CalleeOp);
>
> } else {
> // Direct call.
> @@ -1540,7 +1669,8 @@
> }
>
>
> - MIB = BuildMI(MBB, DL, TII.get(CallOpc)).addGlobalAddress(GV, 0, OpFlags);
> + MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CallOpc))
> + .addGlobalAddress(GV, 0, OpFlags);
> }
>
> // Add an implicit use GOT pointer in EBX.
> @@ -1553,7 +1683,8 @@
>
> // Issue CALLSEQ_END
> unsigned AdjStackUp = TM.getRegisterInfo()->getCallFrameDestroyOpcode();
> - BuildMI(MBB, DL, TII.get(AdjStackUp)).addImm(NumBytes).addImm(0);
> + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(AdjStackUp))
> + .addImm(NumBytes).addImm(0);
>
> // Now handle call return value (if any).
> SmallVector<unsigned, 4> UsedRegs;
> @@ -1580,7 +1711,7 @@
> }
>
> unsigned ResultReg = createResultReg(DstRC);
> - bool Emitted = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
> + bool Emitted = TII.copyRegToReg(*FuncInfo.MBB, FuncInfo.InsertPt, ResultReg,
> RVLocs[0].getLocReg(), DstRC, SrcRC, DL);
> assert(Emitted && "Failed to emit a copy instruction!"); Emitted=Emitted;
> Emitted = true;
> @@ -1594,18 +1725,21 @@
> unsigned Opc = ResVT == MVT::f32 ? X86::ST_Fp80m32 : X86::ST_Fp80m64;
> unsigned MemSize = ResVT.getSizeInBits()/8;
> int FI = MFI.CreateStackObject(MemSize, MemSize, false);
> - addFrameReference(BuildMI(MBB, DL, TII.get(Opc)), FI).addReg(ResultReg);
> + addFrameReference(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
> + TII.get(Opc)), FI)
> + .addReg(ResultReg);
> DstRC = ResVT == MVT::f32
> ? X86::FR32RegisterClass : X86::FR64RegisterClass;
> Opc = ResVT == MVT::f32 ? X86::MOVSSrm : X86::MOVSDrm;
> ResultReg = createResultReg(DstRC);
> - addFrameReference(BuildMI(MBB, DL, TII.get(Opc), ResultReg), FI);
> + addFrameReference(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
> + TII.get(Opc), ResultReg), FI);
> }
>
> if (AndToI1) {
> // Mask out all but lowest bit for some call which produces an i1.
> unsigned AndResult = createResultReg(X86::GR8RegisterClass);
> - BuildMI(MBB, DL,
> + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
> TII.get(X86::AND8ri), AndResult).addReg(ResultReg).addImm(1);
> ResultReg = AndResult;
> }
> @@ -1628,6 +1762,8 @@
> return X86SelectLoad(I);
> case Instruction::Store:
> return X86SelectStore(I);
> + case Instruction::Ret:
> + return X86SelectRet(I);
> case Instruction::ICmp:
> case Instruction::FCmp:
> return X86SelectCmp(I);
> @@ -1728,7 +1864,8 @@
> else
> Opc = X86::LEA64r;
> unsigned ResultReg = createResultReg(RC);
> - addFullAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), AM);
> + addFullAddress(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
> + TII.get(Opc), ResultReg), AM);
> return ResultReg;
> }
> return 0;
> @@ -1758,7 +1895,8 @@
> // Create the load from the constant pool.
> unsigned MCPOffset = MCP.getConstantPoolIndex(C, Align);
> unsigned ResultReg = createResultReg(RC);
> - addConstantPoolReference(BuildMI(MBB, DL, TII.get(Opc), ResultReg),
> + addConstantPoolReference(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
> + TII.get(Opc), ResultReg),
> MCPOffset, PICBase, OpFlag);
>
> return ResultReg;
> @@ -1781,7 +1919,8 @@
> unsigned Opc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
> TargetRegisterClass* RC = TLI.getRegClassFor(TLI.getPointerTy());
> unsigned ResultReg = createResultReg(RC);
> - addFullAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), AM);
> + addFullAddress(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
> + TII.get(Opc), ResultReg), AM);
> return ResultReg;
> }
>
>
> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=107943&r1=107942&r2=107943&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Thu Jul 8 19:39:23 2010
> @@ -1218,13 +1218,12 @@
>
> bool
> X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
> - const SmallVectorImpl<EVT> &OutTys,
> - const SmallVectorImpl<ISD::ArgFlagsTy> &ArgsFlags,
> + const SmallVectorImpl<ISD::OutputArg> &Outs,
> LLVMContext &Context) const {
> SmallVector<CCValAssign, 16> RVLocs;
> CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
> RVLocs, Context);
> - return CCInfo.CheckReturn(OutTys, ArgsFlags, RetCC_X86);
> + return CCInfo.CheckReturn(Outs, RetCC_X86);
> }
>
> SDValue
>
> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=107943&r1=107942&r2=107943&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original)
> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Thu Jul 8 19:39:23 2010
> @@ -740,8 +740,7 @@
>
> virtual bool
> CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
> - const SmallVectorImpl<EVT> &OutTys,
> - const SmallVectorImpl<ISD::ArgFlagsTy> &ArgsFlags,
> + const SmallVectorImpl<ISD::OutputArg> &Outs,
> LLVMContext &Context) const;
>
> void ReplaceATOMIC_BINARY_64(SDNode *N, SmallVectorImpl<SDValue> &Results,
>
> Modified: llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp?rev=107943&r1=107942&r2=107943&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp Thu Jul 8 19:39:23 2010
> @@ -1135,13 +1135,12 @@
>
> bool XCoreTargetLowering::
> CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
> - const SmallVectorImpl<EVT> &OutTys,
> - const SmallVectorImpl<ISD::ArgFlagsTy> &ArgsFlags,
> + const SmallVectorImpl<ISD::OutputArg> &Outs,
> LLVMContext &Context) const {
> SmallVector<CCValAssign, 16> RVLocs;
> CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
> RVLocs, Context);
> - return CCInfo.CheckReturn(OutTys, ArgsFlags, RetCC_XCore);
> + return CCInfo.CheckReturn(Outs, RetCC_XCore);
> }
>
> SDValue
>
> Modified: llvm/trunk/lib/Target/XCore/XCoreISelLowering.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreISelLowering.h?rev=107943&r1=107942&r2=107943&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/XCore/XCoreISelLowering.h (original)
> +++ llvm/trunk/lib/Target/XCore/XCoreISelLowering.h Thu Jul 8 19:39:23 2010
> @@ -193,8 +193,7 @@
>
> virtual bool
> CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
> - const SmallVectorImpl<EVT> &OutTys,
> - const SmallVectorImpl<ISD::ArgFlagsTy> &ArgsFlags,
> + const SmallVectorImpl<ISD::OutputArg> &ArgsFlags,
> LLVMContext &Context) const;
> };
> }
>
> Modified: llvm/trunk/test/CodeGen/X86/fast-isel-loads.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fast-isel-loads.ll?rev=107943&r1=107942&r2=107943&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/X86/fast-isel-loads.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/fast-isel-loads.ll Thu Jul 8 19:39:23 2010
> @@ -5,7 +5,7 @@
> ; CHECK: foo:
> ; CHECK-NEXT: movq %rdi, -8(%rsp)
> ; CHECK-NEXT: movq %rsi, -16(%rsp)
> -; CHECK: movsd 128(%rsi,%rdi,8), %xmm0
> +; CHECK-NEXT: movsd 128(%rsi,%rdi,8), %xmm0
> ; CHECK-NEXT: ret
>
> define double @foo(i64 %x, double* %p) nounwind {
>
> Modified: llvm/trunk/test/CodeGen/X86/fast-isel.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fast-isel.ll?rev=107943&r1=107942&r2=107943&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/X86/fast-isel.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/fast-isel.ll Thu Jul 8 19:39:23 2010
> @@ -49,9 +49,10 @@
> ret i32 %tmp2
> }
>
> -define i1 @ptrtoint_i1(i8* %p) nounwind {
> +define void @ptrtoint_i1(i8* %p, i1* %q) nounwind {
> %t = ptrtoint i8* %p to i1
> - ret i1 %t
> + store i1 %t, i1* %q
> + ret void
> }
> define i8* @inttoptr_i1(i1 %p) nounwind {
> %t = inttoptr i1 %p to i8*
> @@ -86,11 +87,8 @@
> ret i8 %tmp
> }
>
> -define void @store_i1(i1* %p, i1 %t) nounwind {
> - store i1 %t, i1* %p
> - ret void
> -}
> -define i1 @load_i1(i1* %p) nounwind {
> +define void @load_store_i1(i1* %p, i1* %q) nounwind {
> %t = load i1* %p
> - ret i1 %t
> + store i1 %t, i1* %q
> + ret void
> }
>
>
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