[llvm-commits] [llvm] r107851 - in /llvm/trunk: lib/Target/ARM/ARMBaseRegisterInfo.cpp lib/Target/ARM/ARMISelLowering.cpp lib/Target/ARM/ARMInstrInfo.td test/CodeGen/ARM/call-tc.ll test/CodeGen/Thumb2/thumb2-call-tc.ll utils/TableGen/ARMDecoderEmitter.cpp

Evan Cheng evan.cheng at apple.com
Wed Jul 7 21:57:19 PDT 2010



On Jul 7, 2010, at 6:18 PM, Dale Johannesen <dalej at apple.com> wrote:

> Author: johannes
> Date: Wed Jul  7 20:18:23 2010
> New Revision: 107851
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=107851&view=rev
> Log:
> Changes to ARM tail calls, mostly cosmetic.
> Add explicit testcases for tail calls within the same module.
> Duplicate some code to humor those who think .w doesn't apply on ARM.

Thanks Dale. 

Evan

> Leave this disabled on Thumb1, and add some comments explaining why it's hard
> and won't gain much.
> 
> 
> Modified:
>    llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp
>    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
>    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
>    llvm/trunk/test/CodeGen/ARM/call-tc.ll
>    llvm/trunk/test/CodeGen/Thumb2/thumb2-call-tc.ll
>    llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp
> 
> Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=107851&r1=107850&r2=107851&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Wed Jul  7 20:18:23 2010
> @@ -1663,7 +1663,8 @@
> 
>     // Jump to label or value in register.
>     if (RetOpcode == ARM::TCRETURNdi) {
> -      BuildMI(MBB, MBBI, dl, TII.get(ARM::TAILJMPd)).
> +      BuildMI(MBB, MBBI, dl, 
> +            TII.get(STI.isThumb() ? ARM::TAILJMPdt : ARM::TAILJMPd)).
>         addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
>                          JumpTarget.getTargetFlags());
>     } else if (RetOpcode == ARM::TCRETURNdiND) {
> 
> Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=107851&r1=107850&r2=107851&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Wed Jul  7 20:18:23 2010
> @@ -1338,13 +1338,7 @@
>       if (!TII->isLoadFromStackSlot(Def, FI))
>         return false;
>     } else {
> -//      unsigned Opcode = Def->getOpcode();
> -//      if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
> -//          Def->getOperand(1).isFI()) {
> -//        FI = Def->getOperand(1).getIndex();
> -//        Bytes = Flags.getByValSize();
> -//      } else
> -        return false;
> +      return false;
>     }
>   } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
>     if (Flags.isByVal())
> @@ -1400,6 +1394,12 @@
> 
>   // FIXME: Completely disable sibcall for Thumb1 since Thumb1RegisterInfo::
>   // emitEpilogue is not ready for them.
> +  // Doing this is tricky, since the LDM/POP instruction on Thumb doesn't take
> +  // LR.  This means if we need to reload LR, it takes an extra instructions,
> +  // which outweighs the value of the tail call; but here we don't know yet
> +  // whether LR is going to be used.  Probably the right approach is to
> +  // generate the tail call here and turn it back into CALL/RET in 
> +  // emitEpilogue if LR is used.
>   if (Subtarget->isThumb1Only())
>     return false;
> 
> @@ -1409,6 +1409,13 @@
>   // (We could do this by loading the address of the callee into a register;
>   // that is an extra instruction over the direct call and burns a register
>   // as well, so is not likely to be a win.)
> +
> +  // It might be safe to remove this restriction on non-Darwin.
> +
> +  // Thumb1 PIC calls to external symbols use BX, so they can be tail calls,
> +  // but we need to make sure there are enough registers; the only valid
> +  // registers are the 4 used for parameters.  We don't currently do this
> +  // case.
>   if (isa<ExternalSymbolSDNode>(Callee))
>       return false;
> 
> 
> Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=107851&r1=107850&r2=107851&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
> +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Wed Jul  7 20:18:23 2010
> @@ -1049,6 +1049,10 @@
>                        "@TC_RETURN","\t$dst", []>, Requires<[IsDarwin]>;
> 
>     def TAILJMPd : ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
> +                   IIC_Br, "b\t$dst  @ TAILCALL",
> +                   []>, Requires<[IsDarwin]>;
> +
> +    def TAILJMPdt: ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
>                    IIC_Br, "b.w\t$dst  @ TAILCALL",
>                    []>, Requires<[IsDarwin]>;
> 
> 
> Modified: llvm/trunk/test/CodeGen/ARM/call-tc.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/call-tc.ll?rev=107851&r1=107850&r2=107851&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/ARM/call-tc.ll (original)
> +++ llvm/trunk/test/CodeGen/ARM/call-tc.ll Wed Jul  7 20:18:23 2010
> @@ -1,5 +1,5 @@
> -; RUN: llc < %s -march=arm | FileCheck %s -check-prefix=CHECKV4
> -; RUN: llc < %s -march=arm -mattr=+v5t | FileCheck %s -check-prefix=CHECKV5
> +; RUN: llc < %s -mtriple=arm-apple-darwin -march=arm | FileCheck %s -check-prefix=CHECKV4
> +; RUN: llc < %s -march=arm -mtriple=arm-apple-darwin -mattr=+v5t | FileCheck %s -check-prefix=CHECKV5
> ; RUN: llc < %s -march=arm -mtriple=arm-linux-gnueabi\
> ; RUN:   -relocation-model=pic | FileCheck %s -check-prefix=CHECKELF
> 
> @@ -37,3 +37,12 @@
>   %10 = call i32* %9(i32 %0, i32* null, i32 %1, i32* %2, i32* %3, i32* %4) ; <i32*> [#uses=1]
>   ret i32* %10
> }
> +
> +define void @t4() {
> +; CHECKV4: t4:
> +; CHECKV4: b _t2  @ TAILCALL
> +; CHECKV5: t4:
> +; CHECKV5: b _t2  @ TAILCALL
> +        tail call void @t2( )            ; <i32> [#uses=0]
> +        ret void
> +}
> 
> Modified: llvm/trunk/test/CodeGen/Thumb2/thumb2-call-tc.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/thumb2-call-tc.ll?rev=107851&r1=107850&r2=107851&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Thumb2/thumb2-call-tc.ll (original)
> +++ llvm/trunk/test/CodeGen/Thumb2/thumb2-call-tc.ll Wed Jul  7 20:18:23 2010
> @@ -25,3 +25,13 @@
>         %tmp.upgrd.2 = tail call i32 %tmp( )            ; <i32> [#uses=0]
>         ret void
> }
> +
> +define void @j() {
> +; DARWIN: j:
> +; DARWIN: b.w _f  @ TAILCALL
> +
> +; LINUX: j:
> +; LINUX: b.w f  @ TAILCALL
> +        tail call void @f()
> +        ret void
> +}
> 
> Modified: llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp?rev=107851&r1=107850&r2=107851&view=diff
> ==============================================================================
> --- llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp (original)
> +++ llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp Wed Jul  7 20:18:23 2010
> @@ -1578,8 +1578,8 @@
>     // Tail calls are other patterns that generate existing instructions.
>     if (Name == "TCRETURNdi" || Name == "TCRETURNdiND" ||
>         Name == "TCRETURNri" || Name == "TCRETURNriND" ||
> -        Name == "TAILJMPd"  || Name == "TAILJMPdND" ||
> -        Name == "TAILJMPdNDt" ||
> +        Name == "TAILJMPd"  || Name == "TAILJMPdt" ||
> +        Name == "TAILJMPdND" || Name == "TAILJMPdNDt" ||
>         Name == "TAILJMPr"  || Name == "TAILJMPrND" ||
>         Name == "MOVr_TC")
>       return false;
> 
> 
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