[llvm-commits] [llvm] r107600 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/v2f32.ll
Chris Lattner
sabre at nondot.org
Sun Jul 4 15:57:10 PDT 2010
Author: lattner
Date: Sun Jul 4 17:57:10 2010
New Revision: 107600
URL: http://llvm.org/viewvc/llvm-project?rev=107600&view=rev
Log:
fix PR7518 - terrible codegen of <2 x float>, by only marking
v2f32 as legal in 32-bit mode. It is just as terrible there,
but I just care about x86-64 and noone claims it is valuable
in 64-bit mode.
Added:
llvm/trunk/test/CodeGen/X86/v2f32.ll
Modified:
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=107600&r1=107599&r2=107600&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Sun Jul 4 17:57:10 2010
@@ -617,7 +617,12 @@
addRegisterClass(MVT::v8i8, X86::VR64RegisterClass, false);
addRegisterClass(MVT::v4i16, X86::VR64RegisterClass, false);
addRegisterClass(MVT::v2i32, X86::VR64RegisterClass, false);
- addRegisterClass(MVT::v2f32, X86::VR64RegisterClass, false);
+
+ // FIXME: v2f32 isn't an MMX type. We currently claim that it is legal
+ // because of some ABI issue, but this isn't the right fix.
+ bool IsV2F32Legal = !Subtarget->is64Bit();
+ if (IsV2F32Legal)
+ addRegisterClass(MVT::v2f32, X86::VR64RegisterClass, false);
addRegisterClass(MVT::v1i64, X86::VR64RegisterClass, false);
setOperationAction(ISD::ADD, MVT::v8i8, Legal);
@@ -663,14 +668,17 @@
AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v1i64);
setOperationAction(ISD::LOAD, MVT::v2i32, Promote);
AddPromotedToType (ISD::LOAD, MVT::v2i32, MVT::v1i64);
- setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
- AddPromotedToType (ISD::LOAD, MVT::v2f32, MVT::v1i64);
+ if (IsV2F32Legal) {
+ setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
+ AddPromotedToType (ISD::LOAD, MVT::v2f32, MVT::v1i64);
+ }
setOperationAction(ISD::LOAD, MVT::v1i64, Legal);
setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Custom);
setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom);
setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Custom);
- setOperationAction(ISD::BUILD_VECTOR, MVT::v2f32, Custom);
+ if (IsV2F32Legal)
+ setOperationAction(ISD::BUILD_VECTOR, MVT::v2f32, Custom);
setOperationAction(ISD::BUILD_VECTOR, MVT::v1i64, Custom);
setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
@@ -678,7 +686,8 @@
setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i32, Custom);
setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1i64, Custom);
- setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f32, Custom);
+ if (IsV2F32Legal)
+ setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f32, Custom);
setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Custom);
setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom);
setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Custom);
@@ -697,7 +706,8 @@
setOperationAction(ISD::BIT_CONVERT, MVT::v8i8, Custom);
setOperationAction(ISD::BIT_CONVERT, MVT::v4i16, Custom);
setOperationAction(ISD::BIT_CONVERT, MVT::v2i32, Custom);
- setOperationAction(ISD::BIT_CONVERT, MVT::v2f32, Custom);
+ if (IsV2F32Legal)
+ setOperationAction(ISD::BIT_CONVERT, MVT::v2f32, Custom);
setOperationAction(ISD::BIT_CONVERT, MVT::v1i64, Custom);
}
}
Added: llvm/trunk/test/CodeGen/X86/v2f32.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/v2f32.ll?rev=107600&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/v2f32.ll (added)
+++ llvm/trunk/test/CodeGen/X86/v2f32.ll Sun Jul 4 17:57:10 2010
@@ -0,0 +1,16 @@
+; RUN: llc < %s -march=x86-64 -asm-verbose=0 -o - | FileCheck %s
+
+; PR7518
+define void @test1(<2 x float> %Q, float *%P2) nounwind {
+ %a = extractelement <2 x float> %Q, i32 0
+ %b = extractelement <2 x float> %Q, i32 1
+ %c = fadd float %a, %b
+
+ store float %c, float* %P2
+ ret void
+; CHECK: test1:
+; CHECK-NEXT: addss %xmm1, %xmm0
+; CHECK-NEXT: movss %xmm0, (%rdi)
+; CHECK-NEXT: ret
+}
+
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