[llvm-commits] [llvm] r107097 - in /llvm/trunk: lib/CodeGen/SelectionDAG/DAGCombiner.cpp test/CodeGen/ARM/2010-06-28-DAGCombineUndef.ll

[Bob Wilson]

Author: bwilson
Date: Mon Jun 28 18:40:25 2010
New Revision: 107097

URL: http://llvm.org/viewvc/llvm-project?rev=107097&view=rev
Log:
Unlike other targets, ARM now uses BUILD_VECTORs post-legalization so they
can't be changed arbitrarily by the DAGCombiner without checking if it is
running after legalization.

Added:
    llvm/trunk/test/CodeGen/ARM/2010-06-28-DAGCombineUndef.ll
Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=107097&r1=107096&r2=107097&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Mon Jun 28 18:40:25 2010
@@ -2322,7 +2322,8 @@
   }
 
   // fold (or x, undef) -> -1
-  if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) {
+  if (!LegalOperations &&
+      (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)) {
     EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT;
     return DAG.getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT);
   }

Added: llvm/trunk/test/CodeGen/ARM/2010-06-28-DAGCombineUndef.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2010-06-28-DAGCombineUndef.ll?rev=107097&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2010-06-28-DAGCombineUndef.ll (added)
+++ llvm/trunk/test/CodeGen/ARM/2010-06-28-DAGCombineUndef.ll Mon Jun 28 18:40:25 2010
@@ -0,0 +1,10 @@
+; RUN: llc < %s -march=arm -mattr=+neon
+
+define void @main() nounwind {
+entry:
+  store <2 x i64> undef, <2 x i64>* undef, align 16
+  %0 = load <16 x i8>* undef, align 16            ; <<16 x i8>> [#uses=1]
+  %1 = or <16 x i8> zeroinitializer, %0           ; <<16 x i8>> [#uses=1]
+  store <16 x i8> %1, <16 x i8>* undef, align 16
+  ret void
+}