[llvm-commits] [llvm] r106938 - /llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp
Bob Wilson
bob.wilson at apple.com
Fri Jun 25 21:07:15 PDT 2010
Author: bwilson
Date: Fri Jun 25 23:07:15 2010
New Revision: 106938
URL: http://llvm.org/viewvc/llvm-project?rev=106938&view=rev
Log:
Add support for encoding NEON VMOV (from scalar to core register) instructions.
Modified:
llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp
Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=106938&r1=106937&r2=106938&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Fri Jun 25 23:07:15 2010
@@ -139,6 +139,7 @@
void emitMiscInstruction(const MachineInstr &MI);
+ void emitNEONGetLaneInstruction(const MachineInstr &MI);
void emitNEON1RegModImmInstruction(const MachineInstr &MI);
void emitNEON2RegInstruction(const MachineInstr &MI);
void emitNEON3RegInstruction(const MachineInstr &MI);
@@ -413,6 +414,9 @@
emitMiscInstruction(MI);
break;
// NEON instructions.
+ case ARMII::NGetLnFrm:
+ emitNEONGetLaneInstruction(MI);
+ break;
case ARMII::N1RegModImmFrm:
emitNEON1RegModImmInstruction(MI);
break;
@@ -1581,6 +1585,35 @@
return Binary;
}
+void ARMCodeEmitter::emitNEONGetLaneInstruction(const MachineInstr &MI) {
+ unsigned Binary = getBinaryCodeForInstr(MI);
+
+ // Set the conditional execution predicate
+ Binary |= II->getPredicate(&MI) << ARMII::CondShift;
+
+ unsigned RegT = MI.getOperand(0).getReg();
+ RegT = ARMRegisterInfo::getRegisterNumbering(RegT);
+ Binary |= (RegT << ARMII::RegRdShift);
+ Binary |= encodeNEONRn(MI, 1);
+
+ unsigned LaneShift;
+ if ((Binary & (1 << 22)) != 0)
+ LaneShift = 0; // 8-bit elements
+ else if ((Binary & (1 << 5)) != 0)
+ LaneShift = 1; // 16-bit elements
+ else
+ LaneShift = 2; // 32-bit elements
+
+ unsigned Lane = MI.getOperand(2).getImm() << LaneShift;
+ unsigned Opc1 = Lane >> 2;
+ unsigned Opc2 = Lane & 3;
+ assert((Opc1 & 3) == 0 && "out-of-range lane number operand");
+ Binary |= (Opc1 << 21);
+ Binary |= (Opc2 << 5);
+
+ emitWordLE(Binary);
+}
+
void ARMCodeEmitter::emitNEON1RegModImmInstruction(const MachineInstr &MI) {
unsigned Binary = getBinaryCodeForInstr(MI);
// Destination register is encoded in Dd.
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